Model Verification

R2026b

Blocks that verify signals stay within specified bounds during simulation, such as Assertion and Check Static Range

Use blocks from the Model Verification library to check that signals meet specified bounds and conditions during simulation. When a signal violates a verification condition, the block can display a warning, stop the simulation, or both—helping you catch design errors early without writing separate test scripts.

To add blocks from this library to your model, see Add Blocks to Models.

Blocks

	Assertion	Check whether signal is zero
	Check Dynamic Gap	Check that gap of possibly varying width occurs in range of signal's amplitudes
	Check Dynamic Range	Check that signal falls inside range of amplitudes that varies from time step to time step
	Check Static Gap	Check that gap exists in signal's range of amplitudes
	Check Static Range	Check that signal falls inside fixed range of amplitudes
	Check Discrete Gradient	Check that absolute value of difference between successive samples of discrete signal is less than specified value
	Check Dynamic Lower Bound	Check that one signal is always less than another signal
	Check Dynamic Upper Bound	Check that one signal is always greater than another signal
	Check Input Resolution	Check that input signal has specified resolution
	Check Static Lower Bound	Check that signal is greater than (or optionally equal to) static lower bound
	Check Static Upper Bound	Check that signal is less than (or optionally equal to) static upper bound