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Check Dynamic Range

Check that signal falls inside range of amplitudes that varies from time step to time step

  • Library:
  • Simulink / Model Verification

    HDL Coder / Model Verification

  • Check Dynamic Range block

Description

The Check Dynamic Range block checks that a signal falls inside a range of values at each time step and executes an assertion after comparison. The width of the range can vary from time step to time step. The u port is the tested input signal. The min and max ports are the lower and upper bounds of the range, respectively. If u is between max and min, the assertion is true (1) and the block does nothing. If not, the block halts the simulation and returns an error message by default.

The input signals can be scalars, vectors, or matrices. All three input signals must be the same data type. The block compares the value of u to the bounds differently depending on the signal.

  • When comparing scalars to vectors or matrices, the block compares the scalar signal to each element of the non-scalar signal.

  • When comparing vectors or matrix signals to other vectors or matrices, the block checks the inputs element-by-element.

  • For models with more than one vector or matrix input signal, the vectors or matrices must have the same dimensions.

Ports

Input

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Signal specifying the upper bound of the range.

Data Types: half | single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated

Signal specifying the lower bound of the range.

Data Types: half | single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated

Signal checked against the range specified by the max and min ports.

Data Types: half | single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated

Output

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Output signal that is true (1) if the assertion succeeds and false (0) if the assertion fails. If, in the Configuration Parameters window, in the Math and Data Types section, under Advanced parameters, you select Implement logic signals as Boolean data, then the output data type is Boolean. Otherwise, the data type of the signal is double.

Dependencies

To enable this port, select the Output assertion signal parameter.

Data Types: double | Boolean

Parameters

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Clearing this parameter disables the block and causes the model to behave as if the block does not exist. To enable or disable all verification blocks, regardless of the setting of this option, go to the Configuration Parameters window, click Diagnostics > Data Validity, expand the Advanced parameters section, and set Model Verification block enabling to Enable all or Disable all.

Command-Line Information

Parameter: enabled
Type: character vector
Values: 'on' | 'off'
Default: 'on'

Specify a MATLAB® expression to evaluate when the assertion fails. Because the expression is evaluated in the MATLAB workspace, define all variables used in the expression in that workspace.

Dependencies

To enable this parameter, select the Enable assertion parameter.

Command-Line Information

Parameter: callback
Type: character vector
Values: MATLAB expression
Default: ''

Select this parameter to stop the simulation when the check fails. Clear this parameter to display a warning and continue the simulation.

Command-Line Information

Parameter: stopWhenAssertionFail
Type: character vector
Values: 'on' | 'off'
Default: 'on'

Select this parameter to enable the output port.

Command-Line Information

Parameter: export
Type: character vector
Values: 'on' | 'off'
Default: 'off'

Specify the style of the block icon. The graphic option displays a graphical representation of the assertion condition on the icon. The text option displays a mathematical expression that represents the assertion condition.

Command-Line Information

Parameter: icon
Type: character vector
Values: 'graphic' | 'text'
Default: 'graphic'

Block Characteristics

Data Types

Boolean | double | enumerated | fixed point | half | integer | single

Direct Feedthrough

no

Multidimensional Signals

yes

Variable-Size Signals

no

Zero-Crossing Detection

no

Extended Capabilities

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Introduced before R2006a