Vision HDL Toolbox provides flexible interfaces that accept and generate video data as a serial stream of pixel data and control signals. The input and output protocol mimics the timing of a video system, including inactive intervals between frames. Each block or object operates without full knowledge of the image format, and can tolerate imperfect timing of lines and frames.
A separate control bus provides robust synchronization and signaling to handle nonideal timings typically found in real-world systems. You can configure these control signals to support custom and standard resolutions, including 1080p high-definition video.
Vision HDL Toolbox works with both full-frame and pixel-based workflows and provides blocks and objects to perform frame-to-pixel and pixel-to-frame conversions. Toolbox blocks and System objects operate on a pixel, line, or neighborhood rather than on a frame. These blocks enable you to simulate streaming-pixel designs alongside full-frame designs.
Vision HDL Toolbox provides libraries of ready-to-use image and video processing algorithms for FPGA and ASIC implementations. The algorithms have a pixel streaming interface to make it easier to connect algorithms to build a processing pipeline.
The algorithms are designed to process data using onchip line memory to reduce external memory requirements. These algorithms are available as Simulink blocks and System objects to allow bit-true simulation in both MATLAB and Simulink. These blocks and objects support HDL code generation.
Using predefined filters and functions, the toolbox can do the following:
Explore the full list of algorithm blocks in Vision HDL Toolbox.
Vision HDL Toolbox provides libraries of blocks and System objects that support HDL code generation. With HDL Coder you can generate readable, synthesizable VHDL® or Verilog® code for either FPGAs or ASICs. The built-in HDL Workflow Advisor in HDL Coder automatically converts MATLAB code from floating-point to fixed-point code. Using MATLAB and Simulink, you can optimize HDL code to achieve speed-area objectives. HDL Coder also enables you to generate scripts and test benches for use with third-party HDL simulators.
Combining HDL Coder with Vision HDL Toolbox enables the following features:
Using Vision HDL Toolbox with HDL Verifier™, you can use FPGA-in-the-loop to perform real-time simulation and verify implementations with FPGAs. Simulink also provides cosimulation capabilities by connecting with third-party HDL simulators. This enables you to run regressions and test scenarios to ensure precise implementations by comparing HDL implementations with MATLAB algorithms.
HDL verification features enable the following:
When you are ready to prototype your design on FPGA hardware with real-world video input, the Computer Vision System Toolbox™ Support Package for Xilinx® Zynq®-Based Hardware automates the setup and targeting process. This enables you to stream in live video from a supported interface to verify the functionality and performance of your hardware and software processing algorithms.
Support highlights include: