Key Features

  • Video synchronization signal controls for handling nonideal timing and resolution variations
  • Configurable frame rates and sizes, including 60FPS for high-definition (1080p) video
  • Frame-to-pixel and pixel-to-frame conversions to integrate with frame-based processing capabilities in MATLAB® and Simulink
  • Image processing, video, and computer vision algorithms with a pixel-streaming architecture, including image enhancement, filtering, morphology, and statistics
  • Implicit onchip data handling using line memory
  • Support for HDL code generation and real-time verification

Video Interfaces

Vision HDL Toolbox provides flexible interfaces that accept and generate video data as a serial stream of pixel data and control signals. The input and output protocol mimics the timing of a video system, including inactive intervals between frames. Each block or object operates without full knowledge of the image format, and can tolerate imperfect timing of lines and frames.

A separate control bus provides robust synchronization and signaling to handle nonideal timings typically found in real-world systems. You can configure these control signals to support custom and standard resolutions, including 1080p high-definition video.

Using custom and standard resolution sizes to automatically configure timing signals.

Full-Frame and Pixel-Based Processing

Vision HDL Toolbox works with both full-frame and pixel-based workflows and provides blocks and objects to perform frame-to-pixel and pixel-to-frame conversions. Toolbox blocks and System objects operate on a pixel, line, or neighborhood rather than on a frame. These blocks enable you to simulate streaming-pixel designs alongside full-frame designs.

You can use full-frame algorithms, such as those designed using Computer Vision System Toolbox™ or Image Processing Toolbox™, to verify the hardware-targeted design.

Interface blocks to handle frame-to-pixel and pixel-to-frame conversions.

Image and Video Processing Algorithms

Vision HDL Toolbox provides libraries of ready-to-use image and video processing algorithms for FPGA and ASIC implementations. The algorithms have a pixel streaming interface to make it easier to connect algorithms to build a processing pipeline.

The algorithms are designed to process data using onchip line memory to reduce external memory requirements. These algorithms are available as Simulink blocks and System objects to allow bit-true simulation in both MATLAB and Simulink. These blocks and objects support HDL code generation.

Using predefined filters and functions, the toolbox can do the following:

  • Statistics
  • Feature detection
  • Filtering
  • Enhancement
  • Morphological operations
  • Color conversions

Explore the full list of algorithm blocks in Vision HDL Toolbox.

HDL Code Generation

Vision HDL Toolbox provides libraries of blocks and System objects that support HDL code generation. With HDL Coder you can generate readable, synthesizable VHDL® or Verilog® code for either FPGAs or ASICs. The built-in HDL Workflow Advisor in HDL Coder automatically converts MATLAB code from floating-point to fixed-point code. Using MATLAB and Simulink, you can optimize HDL code to achieve speed-area objectives. HDL Coder also enables you to generate scripts and test benches for use with third-party HDL simulators.

Combining HDL Coder with Vision HDL Toolbox enables the following features:

  • Production of target-independent, synthesizable VHDL and Verilog code
  • Code generation support for MATLAB functions, System objects, and Simulink blocks
  • Workflow advisor for programming Xilinx® and Intel® application boards
  • Resource sharing and retiming for area-speed tradeoffs
  • Legacy code integration
Generating synthesizable VHDL and Verilog code from Vision HDL Toolbox with HDL Coder.

HDL Verification and Cosimulation

Using Vision HDL Toolbox with HDL Verifier™, you can use FPGA-in-the-loop to perform real-time simulation and verify implementations with FPGAs. Simulink also provides cosimulation capabilities by connecting with third-party HDL simulators. This enables you to run regressions and test scenarios to ensure precise implementations by comparing HDL implementations with MATLAB algorithms.

HDL verification features enable the following:

  • FPGA-in-the-loop verification using Xilinx and Intel FPGA boards
  • Cosimulation support with Cadence® and Mentor Graphics®
  • Interactive or batch-mode cosimulation and debugging
  • Single-machine, multiple-machine, and cross-network cosimulation

Using FPGA-in-the-loop (FIL) verification to verify HDL designs on Xilinx and Intel FPGA boards.

FPGA Prototyping

When you are ready to prototype your design on FPGA hardware with real-world video input, the Computer Vision System Toolbox™ Support Package for Xilinx® Zynq®-Based Hardware automates the setup and targeting process. This enables you to stream in live video from a supported interface to verify the functionality and performance of your hardware and software processing algorithms.

Support highlights include:

  • Target your video processing algorithms to Zynq hardware from Simulink
  • Stream HDMI signals into Simulink to explore designs with real data
  • Deploy algorithms and visualize data using HDMI output on a screen
  • Connect any HDMI camera source to the FMC-HDMI-CAM card

Prototype your design on FPGA hardware with real-world video input