Festlegen und Überprüfen der Designanforderungen
R2025bSicherheitsanforderungen definieren unerwünschte Verhaltensweisen in einem Modell. Simulink® Design Verifier™ verwendet Eigenschaftsnachweise, um zu überprüfen, ob die mit den Modellanforderungen verbundenen Eigenschaften unter allen möglichen Eingabewerten gelten, oder liefert Gegenbeispiele, die zu Verstößen führen. Sie verwenden Simulink Design Verifier, um Designanforderungen als Eigenschaften zu modellieren, und anschließend Prove Properties in a Model.
Blöcke
 | Proof Assumption | Constrain signal values when proving model properties |
 | Proof Objective | Define objectives that signals must satisfy when proving model properties |
 | Assertion | Prüfen, ob ein Signal null ist |
 | Detector | Detect true duration on input and construct output true duration based on output type |
 | Extender | Extend true duration of input |
 | Implies | Specify condition that produces a certain response |
 | Within Implies | Verify response occurs within desired duration |
 | Verification Subsystem | Specify proof or test objectives without impacting simulation results or generated code |
Funktionen
Themen
Beginnen Sie hier
- Prove Model Properties
Workflow and techniques for proving model properties. - Prove Properties in a Model
Prove model properties that you specify using a Proof Objective block. - Use Parameter Table to Find Constraints
An example of how to specify parameters as variables for analysis. - Specify Signal Ranges
Specify the minimum and maximum value that a signal can attain during simulation. Fully specify your design and optimize data types and the generated code by specifying the minimum and maximum value that a signal can attain during simulation. - Minimum and Maximum Input Constraints
An overview of how the Simulink Design Verifier analysis considers specified input minimum and maximum values. - Specify Input Ranges on Simulink and Stateflow Elements
Describes how the analysis handles minimum and maximum values on Simulink and Stateflow® elements. - Verify and Validate a Model and Code
Define requirements, test models and code, check for design errors and standards compliance, and measure test coverage.
Anforderungsmodellierung für Verifikation und Validierung
- Specify Input Ranges on Simulink and Stateflow Elements
Describes how the analysis handles minimum and maximum values on Simulink and Stateflow elements. - Use Specification Models for Requirements-Based Testing
Follow a systematic approach to verify your design model against requirements. (Seit R2022b)
Verifikation durch Nachweis der Eigenschaften
- Prove Properties in a Model
Prove model properties that you specify using a Proof Objective block. - Property Proving Using Proof Objective Block
You can use Simulink® Design Verifier™ to model design requirements as properties and then prove properties in a model. - Debug Property Proving Violations by Using Model Slicer
Use Model Slicer to debug your design with assertion blocks. - Prove System-Level Properties Using Verification Model
An example that uses a verification model to prove system-level properties. - Check for Specified Minimum and Maximum Value Violations
Describes how to analyze the model to verify that specified design minimum and maximum values are honored. - Property Proving Using MATLAB Function Block
This example shows how to verify the seat belt reminder design model. - Property Proving Using MATLAB Truth Table Block
This example shows how to verify the seat belt reminder design model referenced in the top block above. - Property Proving with an Assumption Block
This example shows how to perform a Simulink® Design Verifier™ property proof using a Proof Assumption block. - Property Proving with an Invalid Property
This example shows how to find an invalid property using Simulink® Design Verifier™ property proving analysis. - Prove Properties in Large Models
Use Simulink Design Verifier workflows and best practices for proving properties in large models.
Enthaltene Beispiele
Validate Requirements by Analyzing Model Properties
Analyze a control system model for adherence to requirements modeled as properties, and investigate property violations by using dependency analysis.
Find and Debug Property Violation Using Simulink Design Verifier
Use Simulink Design Verifier to find and debug property violation in model.
Property Proving Workflow for Thrust Reverser
Verify safety properties in a thrust reverser design model. The Properties block below it contains four safety properties. Simulink® Design Verifier™ analyzes the design model and safety properties to prove correctness or to identify counterexamples. The use of model referencing eliminates the need to add verification content to the design model, allowing the verification content to exist independently from the design.
Property Proving with Multiple Properties
Perform a property proving analysis with multiple properties. The model is configured for the analysis to attempt to prove that:
Property Proving Workflow for Fixed-Point Cruise Control with Block Replacements
Prove properties in a fixed-point cruise control algorithm. It references the design model using model reference so that the original design model is unchanged. A block replacement rule specifies the property that checks if an overflow is possible. The verification subsystem specifies an assumption on the range of the speed input during property proving. This model configures Simulink® Design Verifier™ to apply a block replacement to the Sum block that feeds the outport of the fixed-point PI Controller in the referenced model and return a counterexample that demonstrates an overflow.
Use Observer Reference Blocks for Property Proving Analysis
Perform property proving analysis using Observer Reference blocks.
Prove Properties with Requirements Table Blocks
Use a Requirements Table block and Simulink Design Verifier to prove properties of a model.
