From the series: Vision Processing for FPGA
Vision processing applications often use System-on-Chip (SoC) devices such as those from Xilinx® and Intel®, which allow computationally-intensive tasks running on the hardware to work closely with innovative applications running in software. Learn how to convert data types to fixed point and generate optimized HDL with AXI bus interfaces using the HDL Coder™ IP Core Generation Workflow. Details include:
Select a Web Site
Choose a web site to get translated content where available and see local events and offers. Based on your location, we recommend that you select: .Select web site
You can also select a web site from the following list:
Select the China site (in Chinese or English) for best site performance. Other MathWorks country sites are not optimized for visits from your location.