Videos und Webinare

Vision Processing for FPGA, Part 3: Hardware Design of a Lane Detection Algorithm

From the series: Vision Processing for FPGA

Jack Erickson, MathWorks

The Vision HDL Toolbox^™ lane detection example utilizes many innovative techniques to deliver efficient FPGA hardware using HDL Coder^™. Learn about hardware implementation techniques such as:

Using system knowledge to reduce the amount of computations required in the hardware
Designing custom control logic with a MATLAB^® function block
Computing averages from a stream of data using a rolling window
Redundant “ping-pong” memory buffer to keep pace with the incoming data stream

Product Focus

Series: Vision Processing for FPGA

Part 1: Vision Processing FPGA and ASIC Hardware Considerations Learn about some of the key factors to consider when targeting a vision processing algorithm to FPGA or ASIC hardware.

Part 2: Workflow from a Frame-Based Algorithm to a Pixel-Streaming Implementation Reuse MATLAB vision processing scripts and algorithms to verify a Simulink hardware implementation.

Part 3: Hardware Design of a Lane Detection Algorithm Learn about the hardware implementation techniques used in the Vision HDL Toolbox lane detection example.

Part 4: Targeting a Lane Detection Design to a Xilinx Zynq Device Generate optimized fixed-point HDL to target the lane detection example to FPGA fabric.

Part 5: Hardware-Software Prototyping of a Lane Detection Design Prototype a hardware-software implementation of an automated driving application using the Computer Vision System Toolbox Support Package for Xilinx Zynq-Based Hardware.

Related Products

Vision HDL Toolbox

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Part 4: Targeting a Lane Detection Design to a Xilinx Zynq...

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