Vision Processing for FPGA, Part 3: Hardware Design of a Lane Detection Algorithm

The Vision HDL Toolbox™ lane detection example utilizes many innovative techniques to deliver efficient FPGA hardware using HDL Coder™. Learn about hardware implementation techniques such as: 

• Using system knowledge to reduce the amount of computations required in the hardware 
• Designing custom control logic with a MATLAB^® function block 
• Computing averages from a stream of data using a rolling window 
• Redundant “ping-pong” memory buffer to keep pace with the incoming data stream