Product Requirements & Platform Availability for HDL Verifier

• MATLAB Coder required for using ASIC Testbench for HDL Verifier to generate SystemVerilog DPI or UVM components.
• Simulink Coder required for using ASIC Testbench for HDL Verifier to generate SystemVerilog DPI or UVM components and transaction-level models (TLMs) from Simulink
• Fixed-Point Designer required for cosimulation

Eligible for Use with MATLAB Compiler and Simulink Compiler

No

Eligible for Use with Parallel Computing Toolbox and MATLAB Parallel Server

Yes