LTE HDL Toolbox
Model LTE communications subsystems for FPGAs and ASICs
LTE HDL Toolbox™ provides sample-based algorithms in Simulink® blocks for design and implementation of LTE wireless communications subsystems on FPGAs and ASICs. Toolbox algorithms, gateways between frame-based and sample-based processing, and reference applications enable you to compose an LTE baseband communications subsystem in Simulink.
You can modify the reference applications for integration into your own design. HDL implementations of the toolbox algorithms are optimized for efficient resource usage and performance for prototyping or production deployment on FPGA and ASIC devices.
The toolbox algorithms are designed to generate readable, synthesizable code in VHDL® and Verilog® (with HDL Coder™). For over-the-air testing of LTE designs, you can connect transmitter and receiver models to radio devices (with Communications System Toolbox™ hardware support packages).
Reference Application Hardware Subsystems
Integrate prebuilt and FPGA-proven subsystems to improve your system design efficiency.
LTE Cell Search, MIB, and SIB1 Recovery
Use this subsystem to detect and demodulate eNodeB signals and to decode Master Information Block (MIB) and the System Information Block (SIB1) information for use in your FPGA or ASIC application. It supports FDD and TDD modes and has been proven in hardware to detect LTE signals on three different continents.
Filtered OFDM (F-OFDM) Transmitter
Explore this example to learn how to implement F-OFDM modulation – which is being used in 5G communication systems – in hardware. This technique applies a filter after the inverse fast Fourier transform (IFFT) to improve bandwidth while maintaining the orthogonality of the complex symbols.
Waveform spectrum from the example F-OFDM transmitter.
LTE and Wireless IP Blocks
Design wireless communications subsystems more quickly with hardware-proven streaming algorithms.
LTE IP Blocks
Intellectual property (IP) blocks in LTE HDL Toolbox enable you to model and simulate efficient hardware implementations of LTE-specific algorithms, such as turbo, convolutional, and CRC encoders and decoders as well as OFDM demodulators. You can then use HDL Coder™ to generate synthesizable VHDL or Verilog RTL.
HDL-optimized LTE turbo and CRC decoders with control signal bus.
Multistandard IP Blocks
Use hardware-proven building blocks, such as a Viterbi decoder, a depuncturer, and a variable-size FFT for your hardware implementation of wireless standards, including LTE, WLAN, digital video broadcast (DVB), WiMAX®, and HiperLAN as well as digital satellite communications.
Using Depuncturer and Viterbi Decoder blocks to decode samples encoded at WLAN code rates.
Verification Using Your LTE Golden Reference
Connect frame-based algorithms and test benches to streaming hardware implementations for efficient verification.
Conversion Between Frames and Samples
Convert frame-based waveforms from MATLAB® and LTE Toolbox™ to a stream of samples with control signals for processing in hardware. Then convert the streaming hardware output to frames for verification against your golden reference algorithm.
Frame-to-sample conversion and control signal generation.
MATLAB and Simulink Verification Examples and Templates
Learn how to use your LTE Toolbox algorithms and tests to verify your hardware implementation.
HDL and FPGA Cosimulation
Use HDL Verifier™ to verify your hardware subsystem via RTL simulation or on an FPGA development kit connected to your MATLAB or Simulink test environment.
HDL Verifier supports FPGA-in-the-loop verification using Xilinx®, Intel®, and Microsemi® FPGA boards.
FPGA, ASIC, and SoC Deployment
Easily target your wireless application to FPGA hardware for testing with live over-the-air signals and reuse the same models for production deployment.
Software-Defined Radio (SDR) Platforms
Prototype your wireless application and LTE reference application by downloading the Communications Toolbox™ hardware support packages for Zynq® SDR to set up and target popular SDR devices using HDL Coder™.
Production Deployment
Use HDL Coder to generate high-quality, target-independent RTL and AXI interfaces from your hardware subsystem models.
Generate code with SoC interconnect interfaces.
Latest Features
SIB1 Reference Application
Implement an LTE System Information Block type 1 (SIB1) recovery subsystem on your FPGA or ASIC
Viterbi Decoder and Depuncturer Blocks
Decode convolutionally encoded bit streams using the Viterbi algorithm with puncturing, terminated, and truncated modes
See release notes for details on any of these features and corresponding functions.