Signal Integrity Kits for Industry Standards

Implement industry-standard applications (PCI, DDR, CEI, USB and more) using prepackaged signal integrity kits

Use the prepackaged signal integrity kits to study, analyze, and implement different interfaces such as PCI (peripheral component interconnect), DDR (double data rate), Ethernet, CEI (common electrical interconnect), and USB (universal serial bus). These kits include transmitter and receiver IBIS/AMI models, sample through and crosstalk channels, package models, S-parameter limits, and detailed documentation. You can also reconfigure these kits to meet specific requirements.

Functions

openSignalIntegrityKit Download, extract, and open Signal Integrity Toolbox kits

Topics

Get Started with Signal Integrity Kits
Use signal integrity kits to implement and validate high speed interfaces to meet specified compliance standards or bit error rates.

List of Design Kits

PCIe Kits

PCIe-5 Compliance Kit
Test the compliance of simulation models and topologies to the PCI Express generation 5 (PCIe-5) specification.
PCIe-4 Compliance Kit
Test the compliance of simulation models and topologies to the PCI Express generation 4 (PCIe-4) specification.
PCIe-3 Compliance Kit
Test the compliance of simulation models and topologies to the PCI Express generation 3 (PCIe-3) specification.
PCIe-2 Compliance Kit
Test the compliance of simulation models and topologies to the PCI Express generation 2 (PCIe-2) specification.

CEI Kits

CEI 56G-VSR Compliance Kit
Characterize and validate the performance of a CEI 56G-VSR channel design.
CEI 56G-LR Compliance Kit
Characterize and validate the performance of a CEI 56G-LR channel design.
CEI 28G-VSR Compliance Kit
Characterize and validate the performance of a CEI 28G-VSR channel design.
CEI 28G-SR Compliance Kit
Characterize and validate the performance of a CEI 28G-SR channel design.
CEI 25G-LR Compliance Kit
Characterize and validate the performance of a CEI 25G-LR channel design.
CEI 112G-VSR Compliance Kit
CEI 112G-VSR is a common electrical interface (CEI) implementation agreement that supports 112 Gb/s over “Very Short Reach” (VSR) optical or electrical chip-to-module applications.

Ethernet Kits

10GBASE-KR4 Compliance Kit
Characterize and validate the performance of a 10GBASE-KR4 channel design.
100GBASE-KR4 Compliance Kit
Characterize and validate the performance of a 100GBASE-KR4 channel design.
CAUI-4 Chip-to-Chip Compliance Kit
Test the compliance of simulation models and topologies to the CAUI-4 chip-to-chip (C2C) specification.
CAUI-4 Chip-to-Module Compliance Kit
Test the compliance of simulation models and topologies to the CAUI-4 chip-to-module (C2M) specification.
CAUI/XLAUI Chip-to-Chip Compliance Kit
Test the compliance of simulation models and topologies to the CAUI/XLAUI chip-to-chip (C2C) specification.
CAUI/XLAUI Chip-To-Module Compliance Kit
Test the compliance of simulation models and topologies to the CAUI/XLAUI chip-to-module (C2M) specification.
XAUI Compliance Kit
Characterize and validate the performance of a 10 Gigabit Attachment Unit Interface (XAUI) channel design.

USB Kits

USB 3.1 Compliance Kit
Characterize and validate the performance of a USB 3.1 channel design.
USB 3.0 Compliance Kit
Characterize and validate the performance of a USB 3.0 channel design.

Memory Kits

GDDR6 x32 Architectural Kit
Implement a 32-bit GDDR6 interface for pre-layout analysis or post-layout verification.
GDDR5 x32 Implementation Kit
Implement a 32-bit GDDR5 interface for pre-layout analysis or post-layout verification.
DDR5 Implementation Kit
Implement a 1-slot generic DDR5 RDIMM interface for pre-layout analysis or post-layout verification.
DDR5 IBIS-AMI with Clock Forwarding
This example shows how to use Signal Integrity Toolbox™ for MATLAB to analyze a DDR5 interface with the IBIS-AMI feature Clock-Forwarding enabled for analysis of system margins.
Low-Power DDR5 Architectural Kit
Implement a low-power DDR5 (LPDDR5) interface for pre-layout analysis or post-layout verification.
DDR4 Implementation Kit for JEDEC Raw Card B
Implement a 3-slot DDR4 Raw Card B RDIMM interface for pre-layout analysis or post-layout verification.
Low-Power DDR4 Architectural Kit
Implement a low-power DDR4 (LPDDR4) interface for pre-layout analysis or post-layout verification.
DDR4 Memory Down Implementation Kit
Implement a DDR4 memory down (MD) interface for pre-layout analysis or post-layout verification.
Registered DDR3 Architectural Kit
Implement a Registered DDR3 interface for pre-layout analysis or post-layout verification.
Unbuffered DDR3 Architectural Kit
Implement an unbuffered DDR3 interface for pre-layout analysis or post-layout verification.
Unbuffered DDR3L Architectural Kit
Implement an unbuffered DDR3L interface for pre-layout analysis or post-layout verification.
Registered DDR2 Architectural Kit
Implement a registered DDR2 interface for pre-layout analysis or post-layout verification.
Unbuffered DDR2 Architectural Kit
Implement a registered DDR2 interface for pre-layout analysis or post-layout verification.
Unbuffered DDR2 with PLL Architectural Kit
Implement an unbuffered DDR2 interface with PLL clock buffer for pre-layout analysis or post-layout verification.
RLDRAM III Architectural Kit
Implement a RLDRAM III interface for pre-layout analysis or post-layout verification.
CIO RLDRAM II Architectural Kit
Implement a common I/O (CIO) RLDRAM II interface for pre-layout analysis or post-layout verification.
SIO RLDRAM II Architectural Kit
Implement a separate I/O (SIO) RLDRAM II interface for pre-layout analysis or post-layout verification.
HMC 15G-SR Compliance Kit
Characterize and validate the performance of an HMC 15G-SR channel design.
HMC 30G-VSR Compliance Kit
Characterize and validate the performance of a hybrid memory cube (HMC) 30G-VSR channel design.

Automotive Kits

MIPI D-PHY Serial Link Compliance Kit
Test the compliance of a channel to the MIPI D-PHY specification using Serial Link Designer.
MIPI D-PHY Parallel Link Compliance Kit
Test the compliance to the MIPI D-PHY specification with respect to clock-to-data timing in the forward direction and waveform quality in the reverse transmission using Parallel Link Designer.
MIPI M-PHY Compliance Kit
Characterize and validate the performance of a MIPI M-PHY channel design.

Storage Kits

Fibre Channel FC-PI-6 Compliance Kit
Characterize and validate the performance of a Fibre Channel FC-PI-6 channel design.
QSFP+ Compliance Kit
Test the channel design of a host board for compliance to the QSFP+ specification.
SAS 3.0 Compliance Kit
Characterize and validate the performance of an SAS 3.0 channel design.
SATA 3.0 Compliance Kit
Characterize and validate the performance of a SATA 3.0 channel design.
SFP+ Compliance Kit
Test the channel design of a host board for compliance to the SFP+ specification.