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LPDDR5X Architectural Kit

This example shows you how to implement a Low Power Double Data Rate 5X (LPDDR5X) interface for pre-layout analysis or post-layout verification.

This LPDDR5X architectural signal integrity kit includes transfer nets, mask compliance checks, waveform processing levels and generic IBIS-AMI models for a LPDDR5X interface. This includes generic buffer models for the LPDDR5X controller and SDRAM, along with complete waveform processing levels. You can modify the kit to match your exact LPDDR5X implementation and perform complete pre-layout solution space analysis and/or full post-layout verification for waveform quality and compliance margins.

Open LPDDR5X Kit

Open the LPDDR5X kit in the Parallel Link Designer app using the openSignalIntegrityKit function.


Kit Overview

For more information about the LPDDR5X architectural signal integrity kit, including block diagrams, system configurations, transfer nets and libraries, refer to the document LPDDR5X.pdf that is attached to this example as a supporting file.


[1] JEDEC Standard, Low Power Double Data Rate (LPDDR) 5/5X, JESD209-5C: