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Registered DDR2 Architectural Kit

Implement a registered DDR2 interface for pre-layout analysis or post-layout verification.

This registered DDR2 architectural signal integrity kit includes all transfer nets, timing models, waveform processing levels and generic models for a registered DDR2 interface. This includes generic buffer models for the DDR2 controller, PLL, register, and SDRAM, along with fully functional timing models and complete waveform processing levels. You can modify the kit to match your exact implementation. Then, perform complete pre-layout solution space analysis and/or full post-layout verification for waveform quality and timing margins.

Open Registered DDR2 Kit

Open the registered DDR2 kit in the Parallel Link Designer app using the openSignalIntegrityKit function.



Kit Overview

For more information about the registered DDR2 architectural signal integrity kit, including block diagrams, system configurations, transfer nets and libraries, along with instructions on how to customize the kit for a specific implementation, refer to the document DDR2_Registered.pdf that is attached to this example as a supporting file.

See Also