IP Core

What Is an IP Core?

An IP core—or a semiconductor intellectual property core—is a reusable HDL component in FPGA, programmable system-on-chip (SoC), and ASIC design.

In FPGAs and programmable SoCs, IP cores act as building blocks that you can integrate into complete implementations using design tools such as Vivado™ IP Integrator from AMD or Platform Designer from Intel. The AMBA® AXI version 4 AXI interconnect protocol—better known as AXI4—has emerged as an industry-standard protocol for memory-mapped and streaming data transfer for IP cores.

Schematic showing a reference design with input and output devices and external memory.

IP cores generated by HDL Coder can integrate into custom reference designs generated by SoC Blockset.

You can generate IP cores from MATLAB® code or Simulink® models using the IP core generation workflow in HDL Coder™ with the C/C++ code generation features in Embedded Coder® in an automated hardware-software workflow that targets AMD Zynq™ SoCs and Versal™ Adaptive SoCs as well as Intel® SoC FPGAs.

Using the IP core generation workflow of HDL Coder, you insert your generated IP core into a reference design and generate an FPGA bitstream for the SoC hardware.

These workflows for IP core generation produce custom IP cores that comply with the AXI4 interface supported by AMD and Intel as well as the AXI4-Lite and AXI4-Stream protocols for AMD devices.

A reference design is a predefined embedded system integration project. It contains all elements the Intel or AMD software needs to deploy your design to the SoC platform, except for the custom IP core and embedded software that you generate. You can generate and register a custom reference design manually, or you can use SoC Blockset™ to export custom reference designs automatically from SoC Blockset models in Simulink.

For additional details, see HDL Coder™.

See also: FPGA design and SoC codesign, motor control design with Simulink, AMD Zynq support from Simulink, Intel SoC FPGA support from HDL Coder