Verifying Algorithms on FPGAs and ASICs

CHAPTERS

Chapter 3

Reusing Reference Models in Design Verification

Use HDL Cosimulation to Verify RTL Implementation

Once the MATLAB or Simulink reference model has been completed, hardware designers write or generate RTL to implement the reference model.

HDL cosimulation lets you simulate the RTL back-to-back with the reference model so you can automatically compare results. Portions of the design coded in Verilog^® or VHDL^® are simulated using HDL simulators from Siemens EDA or Cadence^®, with the balance of the design simulated in MATLAB or Simulink.

HDL cosimulation serves as a powerful tool during RTL development since you can use the HDL simulator’s debug environment to identify issues. HDL cosimulation can also be used to assess Verilog or VHDL code coverage, helping you measure your progress toward verification.

Import HDL for Cosimulation with Simulink (5:35)

Generate SystemVerilog Testbench Components from MATLAB or Simulink

You can connect algorithm development to existing verification environments from MATLAB or Simulink.

With direct programming interface (DPI) generation, you specify a MATLAB function or Simulink model as a source, typically for the stimulus or checker of the testbench. You can then generate C code from the source along with a SystemVerilog wrapper that interfaces to simulators from Siemens EDA, Cadence, Synopsys, and AMD through the DPI.

Automatic generation of SystemVerilog testbenches reduces the time that verification engineers spend developing unit tests in SystemVerilog and allows any changes to MATLAB or Simulink golden reference models to be quickly incorporated into RTL testbenches.

Improve RTL Verification by Connecting to MATLAB (41:03)

Generate UVM Environments from Simulink Models

Adopting the Universal Verification Methodology (UVM) can be challenging and time consuming. With the uvmbuild function, you can generate complete UVM environments directly from reference models in Simulink, speeding your adoption of UVM.

Try this example yourself: “Add Random Constraints to Sequences in UVM Testbench”

Through the use of parameterized testbenches, you can generate testbenches that implement constrained-random verification using HDL simulators including Cadence Xcelium™, Synopsys^® VCS^®, Siemens^® Questa^®, and the AMD^® Vivado^® simulator.

“Simulink allows for us to reduce time spent on hand-writing production UVM testbenches, test sequences, and scoreboards by about 50%—leaving more time for us to focus on application for breakthrough innovations.

“Our ASICs designed for automotive applications rely on UVM for production verification—MATLAB and Simulink simplify the once tedious task of developing the algorithms for these devices.”