Antenna Array Simulation and Beamforming for the Expanded GMRT
Kaushal D. Buch, Giant Metrewave Radio Telescope, NCRA-TIFR
Giant Metrewave Radio Telescope (GMRT) is one of the most sensitive instruments in the world for observing celestial objects at radio frequencies. A project proposal called the Expanded GMRT (eGMRT) is aimed at enhancing the scientific capabilities of the GMRT. eGMRT aims to expand the field-of-view of the telescope using a multi-element feed at the focus followed by a beamformer. During the prototype development phase, the team at NCRA-TIFR is building a FPGA-based Focal Plane Array (FPA) beamformer in the L-band with 300 MHz bandwidth and an ability to process 30 independent beams using 144 antenna elements.
The development of the FPA beamformer utilizes MATLAB®, Simulink®, and other MathWorks toolboxes for antenna array simulation, optimization of beamformer weights, FPGA implementation, and data analysis. The simulation of closely-spaced Vivaldi antenna array was carried out using Antenna Toolbox™ and Phased Array System Toolbox™. A GUI-based simulation tool was developed for the simulation of the radiation pattern through user-configurable antenna selection and array configuration. It also helped in understanding the radiation patterns of beams at different offsets from the direction of the main beam and served as a reference for comparison with the results from the practical beamformer testing.
The digital design of the beamformer system was carried out using a model-based approach in Simulink. Xilinx® System Generator blocks were used for implementation of the design. This approach significantly reduced the development time and helped in addressing the incremental changes and debugging.
In this presentation, Kaushal D. Buch describes the array simulation technique, model-based implementation of the beamformer, and recent results from the ongoing prototype development. The presentation also describes how different MathWorks products are useful to a project which uses antenna theory, signal processing, and FPGA design.
Published: 24 Jun 2019