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Tao Jia

MathWorks

Aktiv seit 2012

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I work on HDL Verifier product at MathWorks.

DISCLAIMER: Any advice or opinions posted here are my own, and in no way reflect that of MathWorks.
Professional Interests: FPGA, HDL, Signal Processing, Wireless Communication

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  • Knowledgeable Level 3
  • First Review
  • 3 Month Streak
  • Revival Level 2
  • Knowledgeable Level 2
  • First Answer

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Beantwortet
MATLAB as AXI Master
Please install the following library: https://reference.digilentinc.com/lib/exe/fetch.php?tok=6ec654&media=http%3A%2F%2Ffiles...

mehr als 6 Jahre vor | 0

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MATLAB as AXI Master
Can you provide more information on this? What's your operating system? Windows or Linux? What's your MATLAB version? Can you...

mehr als 6 Jahre vor | 0

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MATLAB as AXI Master
If you are using KC705, then it should work. How did you program the FPGA? There is an on-board USB-JTAG port which uses the...

mehr als 6 Jahre vor | 0

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ModelSim - MATLAB cosimulation not running!!!
First, we need to determine if your ModelSim is 32-bit or 64bit. The easiest way to check this is to look at the title of ModelS...

fast 7 Jahre vor | 1

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problem with simulation tool for HDL Coder when 'cosimulation model' and 'SystemVerilog DPI test bench' is selected
We are supporting Vivado simulator in certain scenarios but not all cases. For example, vivado simulator is supported in the MAT...

etwa 7 Jahre vor | 0

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how to use simulink with modelsim, when ipcore is involved?
The issue is that you'll need to compile the xilinx simulation library first. Then refer to those libraries in your compilation ...

mehr als 7 Jahre vor | 0

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REGARDING CUSTOM FPGA BOARD DEVELOPMENT
Hi Sai, The Genesys 2 board is actually quite different from KC705: # KC705 uses a Marvell Ethernet PHY chip, while Genesy...

mehr als 7 Jahre vor | 1

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Ethernet connexion issue with FIL programmation
Can you manually ping the board? If that works, you can probably ignore the auto validation error. You should be able to run FPG...

mehr als 7 Jahre vor | 0

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Ethernet connexion issue with FIL programmation
I assume that you are using the SGMII mode to connect. In that case, the answer to this question might be helpful: https://ww...

mehr als 7 Jahre vor | 0

Beantwortet
Download bit file to Zynq from HDL Coder
If you know the location of your FPGA programming file, you can always use Vivado to program the FPGA. Also, there is a MATLAB u...

mehr als 7 Jahre vor | 1

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Beantwortet
FPGA is not detected during FIL on Linux
Sounds that the programming of FPGA failed. You need to make sure that FPGA programming is successful before, otherwise you are ...

mehr als 7 Jahre vor | 0

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Fpga-in-the-loop using IP core generation workflow with reference design?
Hi Igor, Currently the IP core generation workflow does not support FPGA-in-the-Loop. If you want to communicate with the...

mehr als 7 Jahre vor | 0

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Beantwortet
filWizard: Error during Validation of Altera Stratix IV GX 230 FPGA development kit
I think your guess might be correct. We do use the Altera Etherent SGMII to GMII IP in your setup. It requires an additional Alt...

mehr als 7 Jahre vor | 0

Beantwortet
The Max Frequency of the signals from MATLAB to FPGA in FPGA-in-the-loop？
Yes, the data exchange rate between MATLAB and FPGA is about 1K samples/second to 5K samples/second for the JTAG communciation t...

mehr als 7 Jahre vor | 0

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Beantwortet
The Max Frequency of the signals from MATLAB to FPGA in FPGA-in-the-loop？
For FPGA-in-the-Loop, you can set the clock frequency of your design. This is done in the filWizard if you are using your own co...

mehr als 7 Jahre vor | 0

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How can I use vhdl generics when I generate a matlab system object from my vhdl code with HDL verifier?
With FPGA-in-the-Loop, once you have generated the FPGA Programming File, the values of generics are fixed. You cannot change it...

etwa 8 Jahre vor | 1

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Beantwortet
Is it possible to test a HDL design with multiple clocks using FPGA-in-the loop and Simulink?
FPGA-in-the-Loop does not support multiple asynchronous clocks. If all your clocks are synchronous, i.e., they are derived from ...

mehr als 8 Jahre vor | 0

Beantwortet
Failed to initialize the RTIOStream library during FPGA-in-the-loop simulation
When you test the board, you need to check "include FPGA Board in the test" checkbox to do a full test. Otherwise, it will not t...

mehr als 8 Jahre vor | 0

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Beantwortet
Does HDL Verifier support FPGA-in-the-loop for BEECube MiniBEE?
Although the HDL Verifier support for BEECube MiniBEE has been discontinued, the user can still run FPGA-in-the-Loop on miniBEE ...

etwa 9 Jahre vor | 1

Beantwortet
zedboard fpga in loop
There is a generic tutorial at: http://www.mathworks.com/help/hdlverifier/examples/verify-hdl-implementation-of-pid-controller-u...

etwa 9 Jahre vor | 1

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Can DE0-Nano-SoC Board from terasic be used with HDL Coder FIL connected using ethernet?
It would take some special action in Qsys to connnect the Ethernet PHY chip to the FPGA fabric. This is not currently supported....

mehr als 9 Jahre vor | 0

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Does FPGA-in-the-loop dump the VHDL code as well as provide data to the board?
During simulation, FPGA-in-the-Loop would provide data to the FPGA board as input, and collect the output at the same time. We'l...

mehr als 9 Jahre vor | 1

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Beantwortet
No FPGA boards listed for HDL Verifier
Hi, The FPGA board definitions for FPGA-in-the-Loop has been moved to hardware support packages since R2013a. This allows us...

etwa 10 Jahre vor | 1

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Beantwortet
Co-simulation with HDL Verifier and ModelSim Altera Edition 10.1d
Unfortunately, there is no workaround. The best way is to use one of the ModelSim versions supported by HDL Verifier, e.g., Mode...

mehr als 10 Jahre vor | 0

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Beantwortet
How to do FPGA-in-the-loop simulation with Altera DE2-115 board?
The switch is the problem. In HDL Verifier documentation, it says that the FPGA board must be connected to the host computer dir...

etwa 11 Jahre vor | 0

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Error in S-function while running FPGA-in-the-loop, FIL Wizard
This looks a problem in the FIL block. Maybe you can check the signals connected to the FIL block (the data type and dimensions)...

etwa 11 Jahre vor | 0

Beantwortet
Xilinx Series 7 Support
Currently HDL Verifier supports Kintex-7 device family and KC705 board. The VC707 board uses a totally different Ethernet interf...

etwa 11 Jahre vor | 0

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Regarding configuremodelsim, It does not configure the selected modelsim
The configmodelsim has been in the deprecation state since 2009a, and it is completed removed in 2012a. Please avoid using this ...

etwa 11 Jahre vor | 0

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FIL Wizard giving me a strange error
This is a known problem, and is fixed in MATLAB 12b.

mehr als 11 Jahre vor | 0

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Is it possible to use ModelSim Code Coverage tools whilst doing an HDL Cosimulation?
Yes, it's definitely supported but you'll have to modify the generated TCL files a little bit (it should be easy). There is ...

mehr als 11 Jahre vor | 0

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