Capture data from live FPGA into MATLAB workspace
The hdlverifier.FPGADataReader
System
object™ communicates with a generated HDL IP core running on an FPGA board to capture
signals from the FPGA into MATLAB®.
The hdlverifier.FPGADataReader
System
object cannot be created directly. To use it, run FPGA Data Capture Component Generator and generate your
own customized FPGADataReader
System
object. You can use the generated object directly or use the wrapper tool, FPGA Data Capture, to set data types and trigger
conditions and capture data.
Before you create the System object, you must have previously generated the customized data capture components. You must also have integrated the generated IP code into your project and deployed it to the FPGA. The object communicates with the FPGA over a JTAG cable. Make sure that the JTAG cable is connected between the board and the host computer.
For a workflow overview, see Data Capture Workflow.
Alternatively, instead of using the step
method
to perform the operation defined by the System
object, you can
call the object with arguments, as if it were a function. For example, y
= step(obj,x)
and y = obj(x)
perform
equivalent operations.
creates a customized object,
DC
= mydcDC
, that captures data from a design running on an FPGA.
mydc
is the component name you specified in the FPGA Data Capture Component Generator app.
clone | Create FPGADataReader System
object with
same property values |
displayDataTypes | Display data types for all captured signals |
displayTriggerSettings | Display overall trigger condition |
isLocked | Locked status (logical) |
launchApp | Capture data from live FPGA into MATLAB workspace, interactively |
release | Release control of JTAG interface |
setDataType | Configure data type for the data captured from a signal |
setTriggerCombinationOperator | Configure operator that combines individual signal value comparisons into overall trigger condition |
setTriggerCondition | Configure each signal value comparison, as a part of overall trigger condition |
step | Capture one buffer of data from HDL IP core running on FPGA |
These examples use a generated object, mydc
,
that defines two signals for data capture. Signal A is
one bit and signal B is 8 bits. Both signals are
also available for use in trigger conditions. The sample depth is
128 samples. The generated HDL IP core is integrated into an existing
FPGA design and running on the FPGA.
Before you open the FPGA Data Capture app, you must have previously generated the customized data capture components, using the FPGA Data Capture Component Generator app. You must also have integrated the generated IP code into your project and deployed it to the FPGA. The app communicates with the FPGA over a JTAG cable. Make sure that the JTAG cable is connected between the board and the host computer.
Create a data capture object using your generated System object. Then open the FPGA Data Capture app.
captureData = mydc; launchApp(captureData)
Create a data capture object and display the default trigger condition. The default configuration of the generated object does not enable any signals as part of the overall trigger condition.
captureData = mydc displayTriggerCondition(captureData)
Trigger Immediately
Display the data types of the captured signals. The default
data type for the 8-bit signal is uint8
.
displayDataTypes(captureData)
Signal Name : Data Type A : boolean B : uint8
Call the object. The data is captured immediately from the FPGA.
dataOut = captureData();
The dataOut
structure contains a field A
,
a vector of 128 logical
values, and a field B
,
a vector of 128 uint8
values.
To debug signal values near a specific event, set up a trigger condition. The trigger condition can be composed of value comparisons of one or more signals. You can combine these value comparisons with only one type of logical operator.
Define a trigger condition to capture data when the FPGA detects
a high value on A
at the same time as signal B
is
equal to 7.
captureData = mydc setTriggerCondition(captureData,'A',true,'High') setTriggerCondition(captureData,'B',true,7) displayTriggerCondition(captureData)
The trigger condition is: A==High and B==7
dataOut = captureData();
dataOut
is returned after the HDL IP core
detects the trigger condition from the signals on the FPGA. dataOut
contains
samples starting from the cycle when the trigger condition is detected.
The default data type for an 8-bit signal is uint8
,
but in your HDL design, it can represent a fixed-point number. Set
the data type of the captured data to cast it to the fixed-point representation.
captureData = mydc
setDataType(captureData,'B',numerictype(1,8,6))
displayDataTypes(captureData)
Signal Name : Data Type A : boolean B : numerictype(1,8,6)
dataOut = captureData();
In the dataOut
structure, field A
is
a vector of 128 logical
values, field B
is
a vector of 128 signed 8-bit fixed-point values, with 6 fractional
bits.