hdlverifier.FPGADataReader System object

Capture data from live FPGA into MATLAB workspace

Description

The hdlverifier.FPGADataReader System object™ communicates with a generated HDL IP core running on an FPGA board to capture signals from the FPGA into MATLAB®.

The hdlverifier.FPGADataReader System object cannot be created directly. To use it, run FPGA Data Capture Component Generator and generate your own customized FPGADataReader System object. You can use the generated object directly or use the wrapper tool, FPGA Data Capture, to set data types and trigger conditions and capture data.

Before you create the System object, you must have previously generated the customized data capture components. You must also have integrated the generated IP code into your project and deployed it to the FPGA. The object communicates with the FPGA over a JTAG cable. Make sure that the JTAG cable is connected between the board and the host computer.

For a workflow overview, see Data Capture Workflow.

Note

Alternatively, instead of using the step method to perform the operation defined by the System object, you can call the object with arguments, as if it were a function. For example, y = step(obj,x) and y = obj(x) perform equivalent operations.

Creation

DC = mydc creates a customized object, DC, that captures data from a design running on an FPGA. mydc is the component name you specified in the FPGA Data Capture Component Generator app.

Properties

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If a trigger condition is enabled, but the HDL IP core does not detect the condition, the data capture request times out after the specified number of seconds. If the data capture is aborted, no data is returned to MATLAB.

When you use the app for data capture, this property is ignored. Use the Stop button on the pop-up window to abort a capture using the app.

Specify the number of recurrences to capture. This value must be a power of two, and cannot be greater than Sample depth. When specifying the sample depth, consider the number of windows you plan to configure when reading the data, because together they impact the window depth of each capture window. The window depth is the Sample depth divided by the Number of capture windows. Specify Sample depth in the FPGA Data Capture Component Generator App.

For example: If Sample depth is 4096 and Number of capture windows is 4, then each capture window has a window depth of 1024.

By default, the clock cycle when the trigger is detected is the first sample of the capture buffer. You can change the relative position of the trigger detection cycle within the capture buffer. A nondefault trigger position means that some samples are captured before the trigger occurs. You can set this parameter to an integer from 0 to window depth–1, inclusive. When the trigger position is equal to window depth–1, the last sample corresponds to the cycle when the trigger occurs. For more information, see Triggers.

If your development board has multiple FPGAs or multiple JTAG connections, the data capture software cannot detect the location of your FPGA in the JTAG chain. Specify these advanced parameters to locate the FPGA that contains the data capture IP core.

Advanced Board Setup

Name of the JTAG cable used for data capture, specified as a character vector. Use this argument when the board is connected to two JTAG cables of the same type

Object Functions

cloneCreate FPGADataReader System object with same property values
displayDataTypesDisplay data types for all captured signals
displayTriggerSettingsDisplay overall trigger condition
isLockedLocked status (logical)
launchAppCapture data from live FPGA into MATLAB workspace, interactively
releaseRelease control of JTAG interface
setDataTypeConfigure data type for the data captured from a signal
setTriggerCombinationOperatorConfigure operator that combines individual signal value comparisons into overall trigger condition
setTriggerConditionConfigure each signal value comparison, as a part of overall trigger condition
stepCapture one buffer of data from HDL IP core running on FPGA

Examples

These examples use a generated object, mydc, that defines two signals for data capture. Signal A is one bit and signal B is 8 bits. Both signals are also available for use in trigger conditions. The sample depth is 128 samples. The generated HDL IP core is integrated into an existing FPGA design and running on the FPGA.

Open the App

Before you open the FPGA Data Capture app, you must have previously generated the customized data capture components, using the FPGA Data Capture Component Generator app. You must also have integrated the generated IP code into your project and deployed it to the FPGA. The app communicates with the FPGA over a JTAG cable. Make sure that the JTAG cable is connected between the board and the host computer.

Create a data capture object using your generated System object. Then open the FPGA Data Capture app.

captureData = mydc;
launchApp(captureData)

Capture Data Immediately

Create a data capture object and display the default trigger condition. The default configuration of the generated object does not enable any signals as part of the overall trigger condition.

captureData = mydc
displayTriggerCondition(captureData)
Trigger Immediately

Display the data types of the captured signals. The default data type for the 8-bit signal is uint8.

displayDataTypes(captureData)
Signal Name : Data Type
A : boolean
B : uint8

Call the object. The data is captured immediately from the FPGA.

dataOut = captureData();

The dataOut structure contains a field A, a vector of 128 logical values, and a field B, a vector of 128 uint8 values.

Capture Data on Trigger Event

To debug signal values near a specific event, set up a trigger condition. The trigger condition can be composed of value comparisons of one or more signals. You can combine these value comparisons with only one type of logical operator.

Define a trigger condition to capture data when the FPGA detects a high value on A at the same time as signal B is equal to 7.

captureData = mydc
setTriggerCondition(captureData,'A',true,'High')
setTriggerCondition(captureData,'B',true,7)
displayTriggerCondition(captureData)
The trigger condition is:
A==High and B==7
dataOut = captureData();

dataOut is returned after the HDL IP core detects the trigger condition from the signals on the FPGA. dataOut contains samples starting from the cycle when the trigger condition is detected.

Capture Fixed-Point Data

The default data type for an 8-bit signal is uint8, but in your HDL design, it can represent a fixed-point number. Set the data type of the captured data to cast it to the fixed-point representation.

captureData = mydc
setDataType(captureData,'B',numerictype(1,8,6))
displayDataTypes(captureData)
Signal Name : Data Type
A : boolean
B : numerictype(1,8,6)
dataOut = captureData();

In the dataOut structure, field A is a vector of 128 logical values, field B is a vector of 128 signed 8-bit fixed-point values, with 6 fractional bits.

Introduced in R2017a