FPGA Data Capture Component Generator

Configure and generate FPGA data capture components

Description

The FPGA Data Capture Component Generator tool configures and generates components for capturing data from a design running on an FPGA. The generated components capture a window of signal data from the FPGA and return the data to MATLAB^® or Simulink^®.

To use this tool, you must have an existing HDL design and FPGA project. To capture the signals, HDL Verifier™ generates an IP core that you must integrate into your HDL project, and deploy to the FPGA along with the rest of your design.

The Generate button in this tool generates these components:

• HDL IP core, for integration into your FPGA design. Connect the signals you want to capture and use as triggers, and connect a clock and clock enable.

• Generation report, with list of generated files and instructions for next steps.

• Tool to set capture parameters and capture data to the MATLAB workspace. See FPGA Data Capture.

• Customized version of the hdlverifier.FPGADataReader System object™ that provides an alternative, programmatic, way to configure and capture data.

• Simulink model that contains a customized FPGA Data Reader block. If you have a DSP System Toolbox™ license, this model streams the captured signals into the Logic Analyzer waveform viewer. Otherwise, the Scope block displays the signals.

For a workflow overview, see Data Capture Workflow.

Open the FPGA Data Capture Component Generator

At the MATLAB command prompt, enter:

generateFPGADataCaptureIP

To reload the parameters of the most recent design, use the restore argument:

generateFPGADataCaptureIP('restore',true);

Examples

Related Examples

• Capture Audio Signal from Intel FPGA Board Using FPGA Data Capture

Parameters

Ports

Port Name — Name of input port on generated IP

character vector | string scalar

The name does not have to match the signal name in your HDL files. This name is used for:

• Input port on the generated HDL IP core. Internal to the IP, this signal is routed to the capture buffer, or to use as part of trigger condition, depending on your selection for Use As.

• Structure field in the captured data returned to the MATLAB workspace

• Port on the generated Simulink block

• Table of signals in the trigger and data types parameters editor at capture time

Data Types: char | string

Bit Width — Number of bits in signal

positive integer

This number is used to generate the HDL IP port definition, and contributes to the total width of the capture buffer. You can specify the data type for the captured data at capture time.

Note

If you do not have Fixed-Point Designer™, data capture can only return built-in data types, such as uint8. You must specify ports for the generated IP that match the sizes of the built-in data types, that is 1, 8, 16, 32, or 64 bits. We recommend Fixed-Point Designer to enable fixed-point data types and captured signals of any size.

Use As — How signal is routed inside IP logic

Both trigger and data (default) | Data | Trigger

When you specify a signal as Data, the signal is captured to the sample buffer and returned to MATLAB, but it cannot contribute to a trigger condition. When you specify a signal as Trigger, it is available for defining a trigger condition at capture time, but is not captured and returned to MATLAB. You can also specify that the signal is used as Both trigger and data.

Target

Generated IP name — Name of generated components

datacapture (default) | character vector

This name is used for the generated HDL IP core, the System object, and the Simulink model.

FPGA vendor — FPGA and software vendor

Altera (default) | Xilinx

The available vendors depend on which HDL Verifier support package you have installed. There are separate support packages for Altera^® and Xilinx^® boards.

Generated IP language — Language used for generated HDL IP core

VHDL (default) | Verilog

Select the language used for the generated HDL IP core as Verilog or VHDL.

Connection type — Type of connection channel

JTAG (default) | Ethernet

Select the type of connection channel as JTAG or Ethernet.

Note

Ethernet connection is available for Xilinx FPGA boards only.

Destination folder — Location to save generated files

hdlsrc (default) | character vector | string scalar

Location to save the generated files, specified as the name of a folder on the host computer.

Data Types: char | string

Capture

Sample depth — Number of samples captured for each signal

128 (default) | 256 | 512 | 1024 | 2048 | 4096 | 8192 | 16384 | 32768 | 65536 | 131072 | 262144 | 524288 | 1048576

Use this parameter to specify the size of the memory in the generated HDL IP core. The width of the memory is the total bit width of the data signals.

When you specify the sample depth, consider the number of windows you plan to configure when reading the data, because together they impact the window depth of each capture window. The window depth is the Sample depth divided by the Number of capture windows. Specify Number of capture windows in the FPGA Data Capture tool.

For example, if Sample depth is 4096 and Number of capture windows is 4, then each capture window has a window depth of 1024.

Max trigger stages — Maximum number of trigger stages for providing trigger conditions

1 (default) | integer from 1 to 10

Use this parameter to enable a sequential trigger. To capture specified data from an FPGA, give a set of trigger conditions in multiple stages.

When you specify the Max trigger stages, consider the maximum number of trigger stages in which you plan to configure the trigger conditions. Specify the number of trigger stages by using the Number of trigger stages parameter in the FPGA Data Capture tool.

For example, if Max trigger stages is 4, then Number of trigger stages can be 1, 2, 3, or 4.