Capture data from live FPGA into MATLAB workspace interactively
The FPGA Data Capture tool captures data from a design running on an FPGA and returns it to the MATLAB® workspace. You can configure the data types of the returned values, specify the number of capture windows and number of trigger stages, and set up a trigger condition to control when the data is captured.
Before using this tool, you must have generated the customized data capture components using the FPGA Data Capture Component Generator tool. You must also integrate the generated IP code into your project and deploy it to the FPGA. The tool communicates with the FPGA over a JTAG cable. Make sure that the JTAG cable is connected between the board and the host computer.
The tool is a wrapper over your generated hdlverifier.FPGADataReader
System object™. The FPGA Data Capture tool
defines the variable, fpgadc_obj
in the workspace. If this variable
already exists, the tool opens using the existing object, and saves modifications to
that object.
For a workflow overview, see Data Capture Workflow.
MATLAB command prompt: Enter launchDataCaptureApp
.
This function is a generated script in the same folder as your other generated
data capture components.
Capture Data
— When to capture dataImmediately
(default) | On trigger
The default setting, capture Immediately
,
ignores any trigger condition and captures the buffer of data when you click
Capture Data. To capture data that includes a
particular event in the FPGA logic, configure a trigger condition and select
On trigger
. In this case, the data capture
logic waits until the trigger condition is true, then captures the buffer of
data.
When you click Capture Data, a window with a Stop button opens. If you want to cancel the capture attempt (for example, if the trigger condition does not occur), click Stop to return control to the tool. When you abort a capture attempt, no data is returned to MATLAB.
Output variable name
— Name of structure in which to return captured dataThe captured data is returned to a structure variable in the base
MATLAB workspace. The data returned from each signal is a vector of
Sample depth
values. Each signal becomes a field in
the structure. The field name in the structure is the same as the
Signal Name.
Display data with Logic Analyzer
— Automatically display data in Logic Analyzeron
| off
This option appears if you have a DSP System Toolbox™ license. When you select this option, after data capture is complete, the tool opens the Logic Analyzer window to display the captured data. The time axes is measured in samples. The cursor location indicates the time the trigger was detected.
Sample depth
— Number of samples captured for each signalThis parameter is read only. It reflects the value you specified at generation time.
Number of capture windows
— Number of data capture recurrences1
(default) | integer power of twoSpecify the number of recurrences to capture. This value must be a power of two, and cannot be greater than Sample depth. When specifying the sample depth, consider the number of windows you plan to configure when reading the data, because together they impact the window depth of each capture window. The window depth is the Sample depth divided by the Number of capture windows. Specify Sample depth in the FPGA Data Capture Component Generator tool.
For example: If Sample depth is
4096
and Number of capture
windows is 4
, then each capture window has
a window depth of 1024
.
Number of trigger stages
— Number of trigger stages for providing trigger conditionsSpecify the number of trigger stages. This value must be an integer from 1 to M, where M is set by the Max trigger stages parameter of the FPGA Data Capture Component Generator tool. When you specify the Max trigger stages parameter, consider the maximum number of trigger stages in which you plan to configure the trigger conditions to capture data.
For example, if Max trigger stages is
4
, then Number of trigger stages
can be 1
, 2
, 3
, or
4
.
Trigger position
— Position of the trigger detection cycle within the capture buffer0
(default) | integer up to window depth -1By default, the clock cycle when the trigger is detected is the first sample of the capture buffer. You can change the relative position of the trigger detection cycle within the capture buffer. A nondefault trigger position means that some samples are captured before the trigger occurs. You can set this parameter to any number from 0 to window depth – 1, inclusive. When the trigger position is equal to the window depth – 1, the last sample corresponds to the cycle when the trigger occurs. If Number of capture windows is greater than one, the same trigger position applies to all windows. For more information, see Triggers.
Trigger combination operator
— Logical operator for creating trigger conditionAND
(default) | OR
This parameter is indicated by the logic gate icon. Press the
Change operator button to toggle between
AND
and OR
.
The trigger condition can be composed of value comparisons
of one or more signals. Combine these value comparisons with only one type
of logical operator. Suppose three signals, A
,
B
, and C
, make up the trigger
condition. The options
are:
A == 10 AND B == 'Falling edge' AND C == 0
A == 10 OR B == 'Falling edge' OR C == 0
Signal
— Trigger component signal nameThis parameter is read only. The signal names you specified at generation time are listed in the drop-down menu at the bottom. Press the + button to add a signal to the trigger condition.
Operator
— Operator to compare signals within trigger condition==
| !=
| <
| >
| <=
| >=
To compare signals, select one of these operators: ==
,
!=
, <
, >
,
<=
, or >=
. To compare signals
containing X
or x
(don't-care value),
specify either ==
or !=
operator.
Value
— Value to compare this signal to, as part of overall trigger conditionLow
| High
| Falling edge
| Rising edge
| Both edges
The trigger condition can be composed of value comparisons of one or more signals. This parameter specifies the value to match for each signal.
For a multibit signal, specify a decimal, binary, or a hexadecimal value
within the range of the data type associated with the signal. While
providing hexadecimal or binary values, you can provide values with a
combination of X
or x
(don't care
value) to enable bit masking. That means, while comparing the values, the
trigger condition discards the place values with X
or
x
and provides the output.
To separate a group of bits for better readability, you can use
_
between bits. For example, you can represent a
32-bit binary value as
0b1010_XXXX_1011_XXXX_1110_XXXX_1111XXXX
and a 32-bit
hexadecimal value as 0xAB_CDEXFX
.
For boolean
signals, select a level or edge condition.
For more information, see Triggers.
Trigger time out
— Maximum number of FDC IP core clock cycles within which trigger condition must occur in a trigger stage1
(default) | integer from 1 to 1,048,576Within this many FPGA Data Capture (FDC) IP core clock cycles, the trigger condition must occur in a trigger stage in which you are enabling this parameter. You can specify any integer value from 1 to 1,048,576 according to your requirements.
Select this parameter to enable trigger time out in a trigger stage. A trigger time out is not allowed in Trigger Stage 1.
Signal Name
— Captured signal nameThis parameter is read only. It reflects the value you specified at generation time. This name is the name of the field in the structure variable.
Bit Width
— Number of bits in the signalThis parameter is read only. It reflects the value you specified at generation time.
Data Type
— Data type for captured datanumerictype
The Data Type menu provides data type suggestions
that match the bit width of the captured signal. This size is the width you
specified for the port on the generated IP. You can type in this field to
specify a custom data type. If the signal is 8, 16, or 32 bits, the default
is uint
. If the signal has one bit, the default is
boolean
. If the signal is a different width, the
default is numerictype(0,bitWidth,0)
.