Configure operator that combines individual signal value comparisons into overall capture condition
Combine Comparisons of Individual Signals into Overall Capture Condition
This example uses a customized data capture object,
DC, that defines two signals for both trigger and data capture.
A is 1 bit and signal
B is 8 bits.
Enable capture condition logic.
DC.EnableCaptureCtrl = true;
To enable capture condition logic, you must select the Include capture condition logic parameter while generating the data capture IP core using the FPGA Data Capture Component Generator tool.
Set up a capture condition to capture data when the FPGA detects a high value on
A at the same time as signal
B is equal to
Combine comparisons of signals
B into an
overall capture condition using an
DC — Customized data capture object
Customized data capture
object, specified as an
hdlverifier.FPGADataReader System object.
operator — Logical operator to combine comparisons of individual signals into capture condition
'AND' (default) |
Logical operator to combine comparisons of individual signals into a capture
condition, specified as
'OR'. The capture
condition comprises value comparisons of one or more signals. To combine value
comparisons, you can use only one type of logical operator. For example, suppose three
C, make up
the capture condition. The options are:
A == 10 AND B == 'Falling edge' AND C == 0
A == 10 OR B == 'Falling edge' OR C == 0
You cannot mix and match the combination operators. For details on capture conditions, see Capture Conditions.
Introduced in R2022a