Configure operator that combines individual signal value comparisons into overall trigger condition
DC— Customized data capture object
Customized data capture
object, specified as an
hdlverifier.FPGADataReader System object.
operator— Logical operator to combine comparisons of individual signals into trigger condition
Logical operator to combine comparisons of individual signals into a trigger
condition, specified as
The trigger condition comprises value comparisons of one or more signals. To combine
value comparisons, you can use only one type of logical operator. For example, suppose
make up the trigger condition. The options are:
A == 10 AND B == 'Falling edge' AND C == 0
A == 10 OR B == 'Falling edge' OR C == 0
You cannot mix and match the combination operators. For details on trigger conditions, see Triggers.
N— Trigger stage
Trigger stage, specified as an integer from 1 to M, where
M is set by the Max
trigger stages parameter of the FPGA Data
Capture Component Generator tool. Use
N to set the
combination operator in
Nth trigger stage. If you do not specify
N, by default, the function sets the combination operator in
trigger stage 1.