Assessments, Criteria, and Verification

Logical and temporal verification, data comparison, value and time tolerances, specialized results processing

Functional testing includes assessing simulation behavior and comparing simulation data to expected results. You can assess simulation behavior by:

Using temporal and logical assessments in a test case.
Including verify statements and other operators in a Test Assessment or Test Sequence block. Use the Test Sequence block to specify a series of steps to stimulate the component or system under test. Use the Test Assessment block to assess the behavior of the component or system under test.
Using blocks from the Model Verification library.

You can assess simulation data by:

Comparing test output to baseline data or comparing the output of two simulations using equivalence criteria.
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Using value or time tolerances when comparing simulation data to baseline data or comparing two simulations. The available types of tolerances are relative, absolute, leading, and lagging. Leading and lagging tolerances are useful for comparisons in which the data timing differs, such as comparisons between different solvers, or comparisons between models running on your desktop and code running on a target.
Using a custom criteria script to process simulation data.

For an overview of the different verification methods, see Assess Simulation and Compare Output Data.

Blocks

Observer Reference	Create and contain an Observer model (Since R2019a)
Observer Port	Wirelessly link signals to use with verification (Since R2019a)
Test Sequence	Create simulation testing scenarios, function calls, and assessments
Test Assessment	Assess and verify behavior of system under test
Sequence Viewer	Display messages, events, states, transitions, and functions between blocks during simulation
Assertion	Check whether signal is zero

`sltest.testmanager.Assessment`	Logical or temporal assessment object (Since R2022a)
`sltest.testmanager.AssessmentSymbol`	Symbol used in assessment (Since R2022a)
`sltest.testmanager.TestCase`	Create or modify test case

Model and code testing in different execution environments, manage test suites, and analyze and report results

verify	Assess logical expression and automatically log result
assert	Evaluate logical expression and stop simulation if false
et	Elapsed time of test step
t	Elapsed time of simulation
after	Elapsed time since beginning of test step
before	Elapsed time until specified time in test step
duration	Elapsed time since beginning of test step
hasChanged	Detect data change in test step
hasChangedFrom	Detect data change from specified value in test step
hasChangedTo	Detect data change to specified value in test step
square	Square wave test signal
sawtooth	Sawtooth wave test signal
triangle	Triangle wave test signal
ramp	Return input value for test signal generation
heaviside	Heaviside step test signal
latch	Save value of an expression

Assess Simulation and Compare Output Data
Assess simulation behavior and compare to expected output, use verify and assert statements and run-time assessments.
Assess Temporal Logic by Using Temporal Assessments
Use temporal assessments to assess model timing and verify temporal signal logic in the System Under Test.
Logical and Temporal Assessment Syntax
Learn about the types of logical and temporal assessments and their syntax.
Assess Model Simulation Using verify Statements
Connect Test Assessment blocks to your model, author verify statements, and verify multiple conditions in the same time step.
Verify Multiple Conditions at a Time
Including multiple verify statements in a single test step using if statements.
Test Sequence and Assessment Syntax
Operators and expressions used in Test Sequence and Test Assessment blocks and Stateflow^® charts.
Access Model Data Wirelessly by Using Observers
Wirelessly access signal and data information.
Observe Messages
Observe message signals and obtain message details.
Observe Conditional Subsystem Signals
Observe signals in conditional subsystems.
Observe Internal Variables of an FMU
Use an observer to access internal variables of an FMU.
Set Signal Tolerances
Specify value and time tolerances for baseline and equivalence criteria.