Komplexe Hardwarebeschreibungen erfolgreich synthetisieren

Bei der FPGA-Programmierung erzeugt man eine Beschreibung der Hardwarestruktur, die dann mit Hilfe von Synthese- und Routingwerkzeugen auf den eigentlichen FPGA-Chip übertragen wird. Diese Hardwarebeschreibung findet typischerweise in speziellen Sprachen wie VHDL oder Verilog statt. Anstelle von FPGA-Programmierung spricht man deshalb auch von einer FPGA-Konfiguration.

Im Gegensatz zur Programmierung etwa von Mikroprozessoren richtet sich die FPGA-Programmierung nicht an einem vorgegebenen Betriebssystem und einer Treiberbasis aus. Sie zielt stattdessen auf die Definition von Strukturen im Halbleiter ab, die später die beabsichtigten Funktionen ausführen. Das ermöglicht einen Spezialisierungs- und Parallelitätsgrad, der von herkömmlichen, vorgefertigten Chips nur schwer zu erreichen ist. Wie leistungsfähig ein programmierter FPGA ist, hängt vor allem davon ab, wie gelungen sein Design ist und damit direkt von seiner effizienten Programmierung.

Das manuelle Arbeiten mit Hardwarebeschreibungen erfordert eine große Erfahrung auf Seiten des Programmierers. Mit zunehmender Komplexität verlangsamt dies die Entwicklungs- und vor allem die Verifikationsprozesse erheblich. Alternativ zum manuellen Entwurf setzen sich darum immer mehr Tools zur FPGA-Programmierung durch, die die Generierung und Verifikation von HDL-Code aus Programmier- und Entwicklungsumgebungen wie MATLAB und Simulink heraus automatisieren.

FPGA-Programmierung mit MATLAB und Simulink

HDL Coder ist das zentrale Werkzeug für die FPGA-Programmierung in der MathWorks-Entwicklungsumgebung. HDL Coder generiert plattformunabhängigen, synthetisierbaren VHDL- und Verilog-Code aus MATLAB-Funktionen, Simulink-Modellen und Stateflow-Diagrammen. Außerdem ermöglicht er die Verifikation des generierten Codes beispielsweise für High-Integrity-Anwendungen nach DO-254 und weiteren Standards durch direkte Rückverfolgbarkeit zwischen Simulink-Modellen und dem daraus generierten Code.

HDL Verifier automatisiert außerdem die Verifikation von VHDL- und Verilog-Designs und macht damit die manuelle Erstellung von Testbenches für VHDL und Verilog überflüssig. Er unterstützt die Anbindung von HDL-Simulatoren von Cadence® Incisive®, Mentor Graphics® ModelSim® und Questa® an MATLAB und Simulink sowie die FPGA-in-the-Loop-Verifikation mit FPGA-Boards von Xilinx und Intel.

Partitioning the elements of your test bench from the algorithm intended for hardware targeting.

The major steps in FPGA programming are:

  1. Hardware architecture design. In the case of an SoC FPGA, the hardware-software SoC architecture.
  2. Design. This is the process of creating the hardware logic itself, typically by writing register-transfer logic (RTL) using a hardware description language (HDL) such as VHDL® or Verilog®. The goal is to match the functionality of the algorithm while operating on a continuous stream of data, using fixed-point operations for efficiency.
  3. Verification. This step ensures that the design works as intended before FPGA programming. This can be as simple as a VHDL or Verilog testbench; commercial projects typically use a methodology such as the Universal Verification Methodology (UVM).
  4. Synthesis. This technology transforms the RTL to digital logic gates and attempts to meet your register-to-register clock frequency goals while minimizing use of the resources on the FPGA.
  5. Integration. An FPGA contains a lot of dedicated resources already—the pins, the clock signal, input/output processing such as analog-to-digital converters (ADC), and interfaces to off-chip memory and other devices on the board. An SoC FPGA also has dedicated registers that both the hardware and software can use to communicate with each other. Your design will need to plug into this “reference design.”
  6. Implementation. This is the process of determining which physical resources on the FPGA to program with which logic, and how to connect (route) them. This produces the bitstream that is loaded onto the device for FPGA programming.
  7. Lab testing and debug. After FPGA programming, you can run using real input or test input. The first few tries often involve figuring out why it does not work and how to fix it. Most of the time this is due to problems in the design step that were not identified in the verification step.

A typical workflow from algorithm design to FPGA programming.

FPGA Programming with MATLAB and Simulink

If you model your algorithms in MATLAB and Simulink, you can focus on designing the algorithm and hardware architecture. The major steps for FPGA programming with MATLAB and Simulink are:

  1. Adding hardware architecture. You will need to adapt your algorithms to add hardware architecture to process a continuous stream of data, typically with fixed-point data types. Simulink offers a time-based visual environment for hardware architecture design. A best practice is to simulate this version of your design and compare the results with your golden algorithm results.
  2. Code generation. Once you have a hardware-ready design, HDL Coder™ generates target-independent Verilog or VHDL RTL with links back to the model for debugging and traceability for functional safety workflows such as DO-254 and ISO 26262.
  3. Integration. You will still need a reference design for HDL Coder to plug your algorithm into for FPGA programming. Many are available as Hardware Support Packages, or from your FPGA board vendor.
  4. Synthesis and implementation. HDL Coder can generate scripts and projects for RTL synthesis, and it has integrated with synthesis and implementation tools from Xilinx, Intel, and Microsemi to provide automated FPGA programming workflows.

Refining your algorithm with hardware detail, then generating synthesizable RTL to target an FPGA development kit or a custom board.

  1. Verification. The simplest way to verify that your RTL functions the same as your algorithm is to use HDL Verifier™ to cosimulate the RTL running in Mentor Graphics® Questa® or Cadence® Xcelium™ together with your design and testbench in MATLAB and Simulink. Be sure to test as many scenarios and corner cases as you can before FPGA programming because debugging on the FPGA provides far less visibility and requires longer iterations. You can use Simulink Test™ to programmatically run and manage your test cases, and Simulink Coverage™ to measure how well you have verified your design.
  2. Lab testing and debug. HDL Verifier enables you to insert logic to drive data into the FPGA from MATLAB as an AXI Master, and to insert logic to capture data from signals internal to the FPGA for debug. You can use MATLAB and Simulink to debug your FPGA directly, whether you are using them for your FPGA programming workflow or not.

Cosimulating your MATLAB and Simulink together with your implemented design running in a supported simulator or on an FPGA board.



Siehe auch: HDL Coder, HDL Verifier

MathWorks Training: Entwicklung von HDL Code aus Simulink

Deploy MATLAB and Simulink Algorithms to FPGAs for Prototyping