What Is ASIC Verification?
ASIC verification is the overall process of testing and verifying the design of an application-specific integrated circuit (ASIC) to ensure that it functions correctly and meets its specifications. Functional verification is the portion of ASIC verification that involves verifying that the digital logic design conforms to its specification.
In many ASIC design teams, system designers use MATLAB® and Simulink® to evaluate and specify new algorithms for ASIC implementation through the use of simulation. The MATLAB code and Simulink models then become specification models for ASIC hardware designers as they develop synthesizable register transfer-level or RTL code, and the MATLAB and Simulink testbenches developed by system designers can be used by ASIC verification engineers as they develop testbenches for unit testing.
Several ASIC verification methods are widely used when specification models and testbenches are developed in MATLAB and Simulink.
ASIC Verification with HDL Cosimulation
Design teams can use MATLAB or Simulink testbenches in combination with HDL simulators in ASIC verification to verify that the RTL is correct using HDL cosimulation. HDL Verifier™ automates this cosimulation process by connecting a MATLAB or Simulink session to an HDL simulator, enabling the two simulators to simulate concurrently and to interchange the values of signals. The MATLAB or Simulink testbench compares output values from the HDL simulator with expected values from a truth model and reports “miscompares.” System designers and ASIC hardware designers can use HDL cosimulation to collaborate in the early stages of ASIC verification.
Exporting SystemVerilog DPI Components for ASIC Verification
The SystemVerilog Direct Programming Interface (DPI) is an interface between SystemVerilog and programming languages such as C. HDL Verifier can generate SystemVerilog DPI components from MATLAB code or Simulink models for use in ASIC verification. These components can then be used with simulators such as Cadence® Xcelium™, Synopsys® VCS®, or Siemens® Questa® where they can serve as stimulus, truth models, or checkers for RTL code in ASIC verification.
Exporting UVM Components and Environments for ASIC Verification
You can generate Universal Verification Methodology (UVM) components or complete UVM verification environments directly from Simulink models. HDL Verifier generates SystemVerilog UVM sequence, driver, monitor, and scoreboard components from models of testbenches for use in ASIC verification. It also produces SystemVerilog files for a behavioral design under test (DUT). The behavioral DUT can then be replaced with manually coded RTL or with RTL generated using HDL Coder™. Generated UVM components and environments may be used with Xcelium, Questa, Xcelium, VCS, and other simulators.
Generating Testbenches with HDL Code Generation for ASIC Verification
Many ASIC design teams utilize HDL Coder to generate RTL to implement new algorithms for ASICs.
If you generate RTL code from a Simulink subsystem using HDL Coder, you can generate a SystemVerilog testbench for ASIC verification. This testbench compares the output of the RTL implementation against the results of the Simulink model.
Alternatively, you can generate a Verilog® testbench for a subsystem when you use HDL Coder to generate RTL. HDL Coder generates a Verilog testbench for ASIC verification by running a Simulink simulation to capture input vectors and expected output data for your DUT. HDL Coder writes the DUT stimulus and reference data from your MATLAB or Simulink simulation to data files.