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Kiran Kintali

Last seen: Today |  Aktiv seit 2011

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Programming Languages:
C++, MATLAB
Spoken Languages:
English, Hindi, Telugu
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He/him

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Beantwortet
How to give random inputs for my simulink design?
You have to wrap the imported Simulink model from HDL Code into a subsystem. Add sources (constants, toworkspace blocks...) an...

3 Tage vor | 0

Beantwortet
Convert Simulink to m file
Correction in the above thread / Accepted Ansswer. Simulink Coder and embedded Coder products support C, C++ code generation...

3 Tage vor | 0

Beantwortet
FPGA Turnkey doesn't update Xilinx Vivado as synthesis tool even after setting tool path
Turnkey workflows are deprecated https://www.mathworks.com/products/hdl-coder.html To target FPGA and SoC devices, use the IP...

3 Tage vor | 0

Beantwortet
MATLAB Function always infers outputs as doubles
It would be hard to reproduce with the partial information above. Sharing a sample MATLAB function supported syntax for HDL cod...

3 Tage vor | 0

Beantwortet
HOW TO: Object detection using automotive RADAR
You should explore HDL Coder based examples in these two products Deep Learning HDL Toolbox: https://www.mathworks.com/help/dee...

4 Tage vor | 0

Beantwortet
Cannot write to AXI-Lite registers [HDL coder, PYNQ, HDL Vision toolbox]
For sobel filter examples using HDL Coder from Simulink consider reviewing these examples. (sampleIn and sampleOut DUT) https:...

9 Tage vor | 0

Beantwortet
I am trying to use "Deploy Neural Network Regression Model to FPGA/ASIC Platform" example
https://www.mathworks.com/matlabcentral/answers/2102651-i-am-trying-to-use-deploy-neural-network-regression-model-to-fpga-asic-p...

16 Tage vor | 0

Beantwortet
How can HDL Code Generation for a full system be performed with System Composer Model that contains multiple Simulink models?
Hi Brad, can you create a support request to help further address this issue? We can followup offline on how to connect System ...

29 Tage vor | 1

| akzeptiert

Beantwortet
Implementing logarithmic function via Simulink HDL Coder
Can you share a bit more about your application and requirements for log? These results can be generated based on your target...

30 Tage vor | 0

Beantwortet
Difference of sine waveform in simulink and real-time
You may find this workflow useful: https://www.mathworks.com/help/hdlcoder/ug/generate-hdl-code-from-simscape-model.html >> whi...

30 Tage vor | 0

Beantwortet
Confused between Hardware to perform Inference
You can follow this example to see how to customize the generated DL Processor with HDL Coder. https://www.mathworks.com/help/d...

etwa ein Monat vor | 1

| akzeptiert

Beantwortet
HDL Coder compatibility issue with Libero SoC 2023.2
It looks like you are using MATLAB R2023b and Libero 2023.2. Please confirm. As per HDL Coder supported versions, you need to...

etwa ein Monat vor | 0

Beantwortet
Loop based error while performing HDL conversion using HDL workflow
Your MATLAB Coding style is incompatible with MATLAB to HDL workflow. Here are few general pointers while we respond to your spe...

etwa ein Monat vor | 0

Beantwortet
Resources utilization for generated HDL code
Please find the attached slides that show how to generate the FPGA Synthesis report from a Simulink model using HDL Coder.

etwa 2 Monate vor | 0

| akzeptiert

Beantwortet
Resources utilization for generated HDL code
This is an estimation report from HDL Coder. >> makehdl('sfir_fixed/symmetric_fir') ### Working on the model sfir_fixe...

etwa 2 Monate vor | 0

Beantwortet
Dataflow Conversion Error when generating hdl code from simulink
This is an unexpected error and seems related to this bug report. https://www.mathworks.com/support/bugreports/3054173

etwa 2 Monate vor | 0

Beantwortet
Is there anyway to test custom IP cores on MATLAB/SIMULINK
You can make a DUT with Simulink subsystems and combine them with your custom IP using Black box interface and the combined IP c...

etwa 2 Monate vor | 0

Beantwortet
IP core generation for built-in Simulink model
Unfortunately we do not have your contact in our tech support database. Can you reach out to our support team via email to suppo...

2 Monate vor | 0

Beantwortet
is there a way to define 'fixdt' in a Matlab script and use this variable in a Simulink User-Defined Function?
Can you share a bit more details of this usecase? A sample model would be helpful. Are you using this in the context of a MATL...

2 Monate vor | 0

| akzeptiert

Beantwortet
Trouble with Vitis Model Composer 2023.2! MATLAB R2021b crashes when I want to open the Model Composer Hub component.
This might be related to a known MATLAB issue: https://www.mathworks.com/matlabcentral/answers/364551-why-is-matlab-unable-to...

2 Monate vor | 0

Beantwortet
IP core generation for built-in Simulink model
Please share your model if possible. I am attaching few sample design patterns that show how to build HDL Coder compliant desi...

3 Monate vor | 0

Beantwortet
what is the difference between FPGA Turnkey and IP Core Generation?
Targeting FPGA & SoC Hardware with HDL Coder Workflow Design a system that you can deploy on hardware or a combination of h...

3 Monate vor | 0

Beantwortet
Force MATLAB code to run on hardware
Please share your code / model that you want to generate HDL from. if you are taking the ML/DL route, please consider https://w...

3 Monate vor | 0

Beantwortet
How to create a simulink model for testbench
You need a testbench and HDL DUT subsystem to generate a valid RTL design and testbench from a Simulink model >> makehdl('l...

3 Monate vor | 0

Beantwortet
Error while generating HDL code from Simulink for Canny Edge Detection
For pure pixel in and pixel out based streaming interface DUT, the blocks such as frame to pixel and pixel to frame should be ou...

3 Monate vor | 0

| akzeptiert

Beantwortet
HDL Coder For Each Subsystem Assertion failed: B:\matlab\src\cgir_hdl\pir_tags\ForEachDataTag.hpp:178:nativeVObj.get()
The error message is not expected. Can you share your model? Either HDL Coder needs to generate code from the model or generate ...

3 Monate vor | 0

| akzeptiert

Beantwortet
How to get the stored integer representation of a single-precision floating point in simulink (HDL Coder)?
https://www.mathworks.com/help/hdlcoder/ref/floattypecast.html Float Typecast Typecast a floating-point type to an unsigned in...

3 Monate vor | 1

| akzeptiert

Beantwortet
wait statement without UNTIL clause not supported for synthesis Error when using HDL coder
Please reach out to tech support if this issue is still reproducible. % Copy the AES demo files to a temporary folder mlhdlc_d...

4 Monate vor | 0

Beantwortet
Matlab code generation and support for Xilinx Cora Z7-07S
HDL Coder doesn't have explicit support for this board, but the closest board that we support looks to be the ZedBoard or ZC702....

4 Monate vor | 0

Beantwortet
SystemC code generation directly from SIMULINK model
HDL Coder generates Synthesizable VHDL, Verilog and SystemVerilog for a DUT in Simulink model for targeting ASIC/FPGA/SoC workfl...

4 Monate vor | 0

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