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Kiran Kintali


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MathWorks

336 total contributions since 2011

Professional Interests: Signal Processing, FPGAs and ESL Design

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Answered
Trenz Electronic TE0820 support in HDL coder toolbox
>> I want to create the algorithm as Simulink models and execute these models in Simulink external mode for debuging and data ga...

11 Tage ago | 0

| accepted

Answered
HDL Code Generation Block Support
HDL Coder specific library in Simulink provides few HDL friendly blocks like RAM, FIFO etc., that are suited for HDL code genera...

11 Tage ago | 0

Answered
Passing HDL parameters through models
This may not yet be supported in HDL block dialogs. Please reach out to support@mathworks.com with your request and usecase mode...

17 Tage ago | 0

Answered
How to generate hdl code for a function containing dsp.HDLFFT and dsp.HDLIFFT system objects?
See the attached file with examples on some of the coding styles. Some of the examples contain FFT variations in MATLAB suitabl...

20 Tage ago | 0

Answered
VHDL Coder Error: variable-size matrix type is not supported for VHDL code generation
Can you check MALTAB to HDL documentation for examples on how to break the design into dut and testbench files? feel free to att...

22 Tage ago | 1

Answered
How to convert this simulink model to VHDL ?
Attached a sample model. Please feel free to share your models. What is the exact frequency and is it a constant or variable wi...

22 Tage ago | 0

Answered
How to build a model using HDL coder library in simulink?
It is quite possible you have installed HDLCoder followed up Xilinx System Generator (XSG) in your machine and some how XSG inst...

26 Tage ago | 0

Answered
hdl coder work flow adviser block compability error
Running hdlsetup command on the model targeted for FPGA always helps in terms of data type selection. web(fullfile(docroot, 'h...

etwa ein Monat ago | 2

Answered
hardware implementation of NN code
Do you have access to these products? https://www.mathworks.com/products/gpu-coder.html GPU Coder™ generates optimized CUDA...

etwa ein Monat ago | 0

| accepted

Answered
How to generate hdl code for a function containing dsp.HDLFFT and dsp.HDLIFFT system objects?
Please share sample MATLAB Code and Testbench and the error you are seeing. Thanks

etwa ein Monat ago | 0

Answered
How to generate hdl code for a function containing dsp.HDLFFT and dsp.HDLIFFT system objects?
Can you share a sample code and testbench? See attached example on how to generate HDL from hdl.FFT function.

etwa 2 Monate ago | 0

Answered
can we generate HDL code for matrix multiplication ?
You can do this to open the models. The models do not use any new 20b features. https://www.mathworks.com/help//simulink/gui/si...

etwa 2 Monate ago | 0

Answered
can we generate HDL code for matrix multiplication ?
Attaching few flavors of matrix multiplication compatible with HDL Coder. matmul_external_memory_20b.slx matmul_mlfb_fixpt_...

etwa 2 Monate ago | 0

Answered
How can I convert from decimal to binary for HDL Coder?
Attaching the model in the example for convenience.

etwa 2 Monate ago | 0

Answered
Data type issue for LUT input
hdlcoderFocCurrentFixptHdl should generate HDL out of the box. >> makehdl('hdlcoderFocCurrentFixptHdl/FOC_Current_Control') ...

2 Monate ago | 0

Answered
hdlcoder std_logic_vector to stateflow type
Attached simple Stateflow chart will generate the code you are looking for.

2 Monate ago | 0

Answered
can we generate HDL code for matrix multiplication ?
hi satish, can you share more details?are both A and B inputs to the DUT or only one of them, what are the types, are you lookin...

2 Monate ago | 0

Answered
HDL-Coder AXI-Vector Strobe Register validation model
HDL Coder does not currently support adding additional logic to the validation model.

3 Monate ago | 1

Answered
HDL Coder: How to create a resettable delay that triggers on rising edge
Please find attached two variations of the model generating HDL code. Simulink “Counter Limited” block with dynamic upper limit...

3 Monate ago | 0

| accepted

Answered
Error with cosimulation on tunable parameters
https://www.mathworks.com/help/supportpkg/xilinxzynqbasedvision/ug/fpga-targeting-workflow.html yes, You can target zed board u...

3 Monate ago | 0

Answered
About hdlsllib/HDL RAMs blocks
>> How can we load data to the RAM or ROM block in simulink?

3 Monate ago | 0

Answered
Error with cosimulation on tunable parameters
This is a limitation in the cosimulation test bench generation. Can you consider using stand-alone testbench with HDL Simulato...

3 Monate ago | 0

Answered
Delay Balancing Error (RTL Code/ IP Core generation)
>> Barry, just to confirm, HDL coder will require disabling delay balancing if the model containts introduced delays inside a fe...

3 Monate ago | 0

Answered
HDL Coder Error: BITAND/BITOR/BITXOR must have matching operand types
HDL Coder team believes this issue has been resolved in the latest releases. Can you share a sample model? We can double check a...

3 Monate ago | 1

| accepted

Answered
Getting Started with Targeting Xilinx Zynq Platform
(follow up from my team) Hi Kiran, I think I might know the issue. In one of the images, I can see the Tool Version text box...

3 Monate ago | 0

Answered
Slow simulation time ins simulink.
“How do I model the clock signal?” – is a question frequently asked by hardware engineers who are new to using Simulink and HDL ...

3 Monate ago | 0

| accepted

Answered
Field oriented control speed controller hdl conversion
Field-Oriented Control of a Permanent Magnet Synchronous Machine In this example you will review a Field-Oriented Control (FOC)...

3 Monate ago | 0

| accepted

Answered
Getting Started with Targeting Xilinx Zynq Platform
The error essage seems to indicate this is an issue with Xilinx Vivado installation? Task "Vivado IP Packager" unsuccessful. ...

3 Monate ago | 0

Answered
HDL Workflow Advisor Error from inf SampleTime
This issue is actively resolved. Please reach out to support@mathworks.com for additional support on this issue. Thanks

3 Monate ago | 0

Answered
HDL coder and Embedded coder interaction
If your target hardware requires you to generate C and HDL code it is better to split your design into two subsystems or two mod...

3 Monate ago | 0

| accepted

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