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When I click on "View Code" after generating Verilog code in HDL Coder, the program doesn't respond.
https://www.mathworks.com/help/hdlcoder/ug/traceability-report.html If you are facing issues with code view please reach out to...
etwa 16 Stunden vor | 0
| akzeptiert
HDL Code Generation Issue – Exceeding IO Pin Count Threshold & MATLAB Freezing
If the generated HDL DUT code results in unreasonable IO, it may eventually lead to failure to meet pin constraint during synthe...
5 Tage vor | 0
SigmoidLayer wont work while implementing on ZC706
Thank you for reporting this. Development team is able to reproduce the issue and will post an update soon.
7 Tage vor | 0
Simulink HDL Coder error when generating
This is an unexpected error handling the if/elseif control structure. Please reach to tech support or share your model here. We ...
20 Tage vor | 0
How can we tune the Discrete integrator of the HDL Coder for second order generalized integrator for FPGA
Can you share the model here or via tech support? Thanks
20 Tage vor | 0
| akzeptiert
Can't register a custom board for the HDL Deep Learning Toolbox
>> Does MATLAB have the option to register a custom board? Yes, You can see the doc here https://www.mathworks.com/help/hdlcode...
21 Tage vor | 0
How do I configure HDL Coder so that it recognizes my Vivado version?
Please review this post that is relevant here. https://in.mathworks.com/matlabcentral/answers/518421-which-versions-of-vivado-a...
21 Tage vor | 0
| akzeptiert
What's the most suitable Vivado version for Matlab 2025a
This example shows how to model, partition, and deploy a design that leverages the processor, FPGA, and AI Engines on a Versal d...
22 Tage vor | 0
| akzeptiert
MATLAB HDL-Coder: Expression could not be reduced to a constant.
Is hwconst an input variable (creates hardware interface pins) or just a non-tuanble constant parameter passed into the design...
30 Tage vor | 0
| akzeptiert
Troubleshooting Signal Logging in SDI for FPGA Outputs in Speedgoat Motion Control HDL I/O Blockset
Klemen, Thanks for reporting this. Our support team at Speedgoat is reviewing the issue and respond here shortly.
etwa ein Monat vor | 1
How to resolve unsupported functions in MATLAB HDL Coder?
Happy to assist you with your MATLAB to HDL workflow. Attached is a sample zip file with the code for the attached functions (us...
etwa ein Monat vor | 0
Error evaluating parameter. Dot indexing is not supported for variables of this type.
Can you please share your model here or reach out to tech support? The following message is not expected and a better message ne...
etwa 2 Monate vor | 0
Matlab for my needs
https://www.mathworks.com/help/hdlcoder/examples.html https://www.mathworks.com/help/hdlcoder/run-and-verify-generated-ip-cor...
2 Monate vor | 0
Is it possible to integrate the HDL CODE generated by simulink into an existing user-defined vivado project?
Generating an IP core wrapper for the HDL Coder generated code is the best way to integrate your algorithm into an existing vi...
2 Monate vor | 1
Ultra RAM on True Dual Port RAM
Please do attach your sample model as a test case. This is a known issue and HDL Coder R&D team have reported the issue to Viva...
3 Monate vor | 0
| akzeptiert
Using fixed FPGA capacity for a variable number of Simulink signal channels
Have you considered tunable parameter usage in HDL Coder? https://www.mathworks.com/help/hdlcoder/ug/generate-code-for-tunable-...
3 Monate vor | 0
HDL Coder "Error using find Too many input arguments."
Based on the error message this issues seems to be related to report generation infrastructure failure. The issue is resolved in...
3 Monate vor | 0
Do the additional delays added by adaptive pipeline distroy the alignment between signal paths?
Please share your release. Adaptive Pipelining is an optional feature. When enabled it tries to improve timing of your design. ...
4 Monate vor | 0
Deep Learning HDL Toolbox + Quartus Pro 23.3
Please check the HDL Coder supported version of Intel Quartus with R2024a and R2024b releases. https://www.mathworks.com/help/r...
4 Monate vor | 0
how to download the third party support package file "xilinx linux binaries"
What version of MATLAB are you using? Please do not hesitate to reach out to tech support.
4 Monate vor | 0
Seeking Guidance on Auto-Generating Verilog Code for ASIC Simulation with HDL Coder and Deep Learning HDL Toolbox
Classify ECG Signals Using DAG Network Deployed to FPGA This example shows how to classify human electrocardiogram (ECG) signal...
5 Monate vor | 0
Characterisation error in HDL code generation?
This is an unexpected error. What version of MATLAB are you using? Can you share the model? Do not hesitate to reach out to te...
5 Monate vor | 0
Why do I receive a privimporthdl error when importing the operator.vhd example
VHDL Import is a new feature in R2024b release. https://www.mathworks.com/help/releases/R2024b/hdlcoder/release-notes.html?star...
5 Monate vor | 0
how to find abc_expected.dat file in MATLAB simulink model ?
HDL Coder generates RTL code (VHDL, Verilog, SystemVerilog) from the Design Under Test. It can also generate a RTL testbench f...
6 Monate vor | 0
| akzeptiert
Problem related to GUI deployment
In a fresh launch of MATLAB session repeat the above steps. When the error hits run the following command >> license inuse you...
6 Monate vor | 0
| akzeptiert
struct memeber can not be Simulink.Parameter?
These pages contain good info on allowed ExportedGlobal usage in HDL Coder https://www.mathworks.com/help/hdlcoder/ug/generate-...
6 Monate vor | 0
generated rs code function result is not different with matlab simulink simulation
Are you using HDL Coder with this demo and not meeting timing? https://www.mathworks.com/help/wireless-hdl/ug/rsdecode.html op...
6 Monate vor | 0
How to properly use hdl.RAM for Matlab to VHDL conversion?
HDL Coder generated code should match the fixed point code. I see you are using coder.hdl.pipeline which are pipeline delays and...
6 Monate vor | 0
HDL Coder; Matlab Function Blocks and Clocked Processes
For a subset of MATLAB with data flow semantics you may find MATLAB Function Block (Data Path Architecture) more suitable for ...
7 Monate vor | 0
zcu102: split tasks between the 4 available CPUs
https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-hardware-software-codesign-workflow-for-zynq-ultrascale-mpsoc-...
7 Monate vor | 0
