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Assertion Error in HDL Coder
This is not an expected error from the product. Can you please provide the reproduction steps with support team? We will try to ...

4 Monate vor | 0

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Multiple IOSTANDARDs for a single HDL coder interface
https://www.mathworks.com/help/hdlcoder/ref/hdlcoder.board.addexternaliointerface.html addExternalIOInterface('InterfaceID',int...

4 Monate vor | 1

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Error running simulink with QuestaSim. Failed to connect to server. Make sure loaded HDL simulator library is using shared memory.
It looks like you are generating cosimulation model from HDL Coder. The issues seems related to either installation of the HDL...

5 Monate vor | 0

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HDL FIFO Reset Problem
Would you be able to share your sample model? You can prune it to just show HDL FIFO block. Found a relevant report here. Need ...

5 Monate vor | 0

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Error while using vector real gateway in
https://www.xilinx.com/products/design-tools/vitis/vitis-model-composer.html This issue needs to be posted to AMD tech suppor...

6 Monate vor | 0

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Delay balancing error using R2023b, but have not experienced this in R2017b
The model fails code generation due to pipeline requests at the faster rate that need to be balanced. Need to review generated...

6 Monate vor | 0

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How do i define an array as a HDL input?
It would be helpful to share your model. HDL Coder supports vector inputs at the DUT interface. Attached is an example of 40poi...

6 Monate vor | 2

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add_block from other toolboxs
Run this command to see the supported block list. >> hdllib('html') ### HDL supported block list hdlblklist.html ### HDL impl...

6 Monate vor | 0

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Scalarize Vector Ports option get the HDL code running time is infinite
You have unsynthesizable IO in your model. Please consider IO optimization to convert the frame model to sample model manually o...

6 Monate vor | 0

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From Simulink to Vivado
Closing the thread. This error is not reproducible since 2019a release. Please reach out to tech support if you see the issue...

6 Monate vor | 0

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How can i generate a triangular wave form using HDL supported blocks
See the attached sample model (with updown carrier type) you can generate triangular wave. Some examples you may also find ...

6 Monate vor | 0

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SIMULINK - HDL code generation with floating point & matlab function block
This restriction is relaxed since R2019b. Simulink Blocks Supported by Using Native Floating Point https://www.mathworks.com/...

6 Monate vor | 0

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Icc64.exe has stopped working
Please check the supported compilers here https://www.mathworks.com/support/requirements/supported-compilers.html Please note a...

6 Monate vor | 0

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Get inverse of scalar in hdl code generation
There are multiple ways to generate HDL from HDL with reciprocal and divide operators. If the scalar variable you are computin...

6 Monate vor | 0

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IP core generation fails with vivado error
Closing this unanswered thread. This issue is resolved starting R2016a release. Please reach out to tech support if you see th...

6 Monate vor | 0

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Generate a PWM in FPGA using a customised carrier.
There are several pulse generator blocks in the Simulink library that are on the HDL Coder roadmap for automatic code generation...

6 Monate vor | 0

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Dynamic LUT in HDL coder
LUT with BP data as an input is a work in progress feature in HDL Coder. Reach out to tech support for your requirements. Unt...

6 Monate vor | 0

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about the Deep Learning HDL Toolbox Support
You can customize and target the DL HDL Toolbox generated code for any FPGA/ASIC/SoC hardware including Xilinx/AMD devices. h...

6 Monate vor | 0

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fimath error in hdl coder
I am assuming you are using MATLAB code to HDL or MATLAB Function Block in Simulink. Can you share your sample model? Usually f...

6 Monate vor | 0

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Xilinx ZCU102 not booting with pre-built image
This could be FSBL related error unrelated to HDL Coder. Found several references here. I will try to research a bit more. Pleas...

6 Monate vor | 0

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Sending waveform specifications from matlab to fpga
Please reach out to tech support or share a sample testbench (that generates the MRI waveform) and design (intended for FPGA) fo...

7 Monate vor | 0

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How to disable clockdriver logic and clr port (automatic added) in generated vhdl code?
This is an integraiton workflow between HDL Coder from MathWorks along with Xilinx System Generator (XSG) from AMD. https://ww...

7 Monate vor | 0

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Bug related to using selector block with complex data type in HDL code generation
Can you share your sample model and the release of MATLAB you are encountering this error? Please find the attached model and t...

7 Monate vor | 0

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Estimate the resource utilization for custom board that has the Kintex7 chip family
This is a known issue and is being actively resolved. It is due to a bug in the format of the device list for Kintex7 family...

7 Monate vor | 0

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HDL code generation for FFT
If you are looking for MATLAB coding style for generating HDL using HDL Coder you can find some samples here. https://www.mat...

7 Monate vor | 0

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matlab code for hdl conversion
HDLCoder Design Patterns and Examples This link has several tutorials in this submission show how to generate HDL from MATLAB...

7 Monate vor | 0

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Native floating-point latency and adding delay block.
You can just model the math and let HDL Coder figure out how to pipeline the design. >> makehdl('dut_nfp/Su...

7 Monate vor | 1

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Failed Internal Error: Could not connect the blocks in the model during HDL Code generation
This usually indicates the model cannot be put in a compiled state prior to HDL Code generation. You should consider restart...

7 Monate vor | 0

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How can I connect fpga board basys3ᵀᴹ to Matlab simulink ?
You can use this example as a reference to create a workflow for your Basys Board. https://www.mathworks.com/help/hdlcoder/ug/d...

7 Monate vor | 0

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How to implement a digital control transfer function on an FPGA using HDL coder?
Have you considered realizemdl function to generate a Simulink and using HDL Coder to generate code from the Simulink model? ...

7 Monate vor | 0