photo

Michael Du


Last seen: mehr als 4 Jahre vor |  Aktiv seit 2019

Followers: 0   Following: 0

Statistik

  • Thankful Level 1
  • First Answer
  • Revival Level 1

Abzeichen anzeigen

Feeds

Anzeigen nach

Beantwortet
Rate transitions and HDL generation port requirement
Ferrara, Thank you for your instruction. I have been updating the rate transition at the input or output ports or internal logi...

fast 5 Jahre vor | 0

Beantwortet
Rate transitions and HDL generation port requirement
The model is attached. To simulate the functionality, it reads in a captured data file and serialize them outside the HDL conver...

fast 5 Jahre vor | 0

Frage


Rate transitions and HDL generation port requirement
Due to the down-sampling requirement, the rate transition HDL block is used to sample at a lower rate of the data stream. Also, ...

fast 5 Jahre vor | 4 Antworten | 0

4

Antworten

Frage


HDL IP block with more than one type of AXI interface
The idea is to generate the HDL IP blocks using the external PL DDR3 memories with both AXI4 Master and AXIS interfaces. The dat...

fast 5 Jahre vor | 1 Antwort | 0

1

Antwort

Frage


AXI4-S interface must use the same sample rate
This question is for the HDL advisor workflow. The AXIS data slave input of the system are taking in data from 3 channels, packa...

fast 5 Jahre vor | 0 Antworten | 0

0

Antworten

Beantwortet
Serial port timeout- 10 seconds, but getting less samples than expected/desired
I have similar questions. Matlab seems to set an upper limit to the serial port timeout of ~20ms and the serial input size of 2k...

fast 5 Jahre vor | 0