AXI4-S interface must use the same sample rate

This question is for the HDL advisor workflow. The AXIS data slave input of the system are taking in data from 3 channels, package them into the AXIS data input, then the IP block deserialize them into 3 channels of 16 bit data, and some algorithm calculation are performed with these 3 channels of data. The AXIS data outputs are a pair of 16 bits data and they are grouped into the AXIS Master out data. The interface mapping and high level system block are attached. During HDL flow conversion, it failed at the sample rate statement as "AXI4-S interface must use the same sample rate". I don't quite understand, because all the input data are running at the same clock rate and there is no rate transition used in the HDL simulink models.

Could you point out the reason for the rate conversion error?