Bharath Venkataraman
Statistiken
0 Fragen
275 Antworten
RANG
230
of 281.600
REPUTATION
384
BEITRÄGE
0 Fragen
275 Antworten
ANTWORTZUSTIMMUNG
0.00%
ERHALTENE STIMMEN
36
RANG
of 19.054
REPUTATION
N/A
DURCHSCHNITTLICHE BEWERTUNG
0.00
BEITRÄGE
0 Dateien
DOWNLOADS
0
ALL TIME DOWNLOADS
0
RANG
of 133.885
BEITRÄGE
0 Probleme
0 Lösungen
PUNKTESTAND
0
ANZAHL DER ABZEICHEN
0
BEITRÄGE
0 Beiträge
BEITRÄGE
0 Öffentlich Kanäle
DURCHSCHNITTLICHE BEWERTUNG
BEITRÄGE
0 Highlights
DURCHSCHNITTLICHE ANZAHL DER LIKES
Contribute at least one answer each month for 12 consecutive months
Awarded to Bharath Venkataraman on 16 Nov 2017
Answer 3 questions that were unanswered for more than 30 days
Awarded to Bharath Venkataraman on 20 Jul 2017
20 of your answers have been accepted
Awarded to Bharath Venkataraman on 20 Jul 2017
Provide your first answer ever to someone else's question
Awarded to Bharath Venkataraman on 20 Jul 2017
Content Feed
Multiple Simulink runs only changing signal vector
This example shows how to accelerate BER measurements for HDL LTE Turbo Decoder model with data from MATLAB feeding a Simulink m...
3 Tage vor | 0
| akzeptiert
HDL Coder fails to generate VHDL...Assertion Failed With Debug Message: B:\matlab\src\cgir_hdl\hdl_emitters\VHDLPIREmitter.cpp:1715:assignExpr: Component 's output signal
I suggest contacting MathWorks Support - we may need the model to debug what is causing the error.
3 Tage vor | 0
How can I setup the "FIR Rate Conversion HDL Optimized" block to give an evenly distributed output without the need for a FIFO?
This block provides output as soon as it is able to, so the output is not evenly spaced. You will need a small FIFO in this case...
etwa 2 Monate vor | 0
| akzeptiert
Error editing outputframe of Implement Digital Upconverter example
Attached is a model (DUCforLTEHDL_14bit_v2_23a) that works around the issue found in the way the FIR Interpolator sends out outp...
etwa 2 Monate vor | 0
Do i need to add a LUT-lookup table along with the hdlNCO block to perform a frequency shifting. if yes, please give clear guidance with the blocks and passing parameters
Kranti has answered this question in this post. Please take a look at that answer where he points to the Coarse Frequency Compen...
etwa 2 Monate vor | 0
| akzeptiert
Please help me fix Digital Upconverter filter problem
I was able to update the MATLAB script and model to reduce the wordlength and fraction length by 2 bits (keeping the same headro...
2 Monate vor | 0
How to pass the complex double values as the fixed point values to the "NCO" block to generate the HDL code. many entries are in NCO, what vals & wht prt of scipt are added?
If the shift value is constant, you can set the phase increment source to Property. The value of the phase shift should be 2^QUA...
2 Monate vor | 0
| akzeptiert
The function of generating HDL code has an error with the names of blocks in the same Subsystem
There is a configuration statement in line 101 which maps whdlOFDMTx to use the entity work_whdlOFDMTx.whdlOFDMTx_whdlOFDMTx(rtl...
2 Monate vor | 0
How to pass complex double value of array in the workspace to "HDL FFT block-DSP HDL toolbox block" to generate HDL code
I assume the data you are showing is for a 512 point FFT and you have 20 frames of data. I would first serialize this data usin...
2 Monate vor | 0
| akzeptiert
Please, if anyone knows please help me to debug this "Error in OFDM (line 20) info = h5gOFDMInfo(genb);"
Hi @Ho, Could you tell us which version of MATLAB you are using? If you open the Filtered OFDM example using openExample, the ...
2 Monate vor | 0
how to build a Simulink HDL block set for FREQUENCY SHIFTING process with a for loop in the MATLAB
The NCO HDL Optimized block along with a multiply block can be used to generate the shift.
3 Monate vor | 0
| akzeptiert
can you tell me what is the use of Pack Data IP --> Pack vector and how is it working?
I believe this code uses bitconcat to concatenate all the elements of the vector into a single unsigned value. u(1) becomes the...
3 Monate vor | 0
How to restart ModelSim simulation after each iteration from MATLAB script co-simulation?
I believe Marc's suggestion is to close ModelSim after every run of Simulink and reopen it. To start ModelSim, you typically us...
3 Monate vor | 0
| akzeptiert
scalarize vector ports in generation vhdl code with hdl coder
I suspect that you are sending in the entire frame of video into the median filter at one shot. I suggest you stream the video i...
5 Monate vor | 0
How to efficiently manage control signals, such as ValidIn or StartIn, for HDL blocks?
There are a variety of ways to do this. As you have noted, you can use Simulink block like the pulse generator to drive these s...
5 Monate vor | 0
| akzeptiert
How do I resolve missing block/HDLImplementation pair
This may be an installation issue. Please contact MathWorks support: https://www.mathworks.com/support/contact_us.html
6 Monate vor | 0
implementation of median filtre on FPGA ?
You could use the Median Filter block or the visionhdl.MedianFilter System object in Vision HDL Toolbox, which offer this capabi...
6 Monate vor | 0
Looking for MATLAB and Simulink file for OFDM Model Tx, Rx and Reference Models
You will need the Wireless HDL Toolbox to be able to download these models. The models are in the Examples section of that Toolb...
7 Monate vor | 0
Cyclic Prefix Removal OFDM FFT IEEE802.11
Setting the valid input low for the first 16 samples as shown above will tell the FFT block to ignore those samples. The FFT bl...
7 Monate vor | 0
How to convert the Simulink project to VHDL code?
You can run the hdlsetup function on the model to set the parameters of the model to common default values for HDL code generati...
7 Monate vor | 0
Verify the Verilog generated by HDLcoder
You can use the Generate Testbench feature of HDL Coder to generate an HDL testbench that takes the simulation input and output ...
7 Monate vor | 0
The Simulink model is fixed-point based on floating-point numbers
You can put a breakpoint in the MATLAB Function block to see whee the code is generating the double output. See this link on how...
7 Monate vor | 0
How to use the FFT block of Vitis Model Composer
"Vitis Model Composer" is a third-party blockset provided by Xilinx, so it is best to reach out to Xilinx technical support if y...
8 Monate vor | 0
Remainder of a division operation in System Generator
When you say "running value", what is the range of the update value? If the initial value can be set to the proper range of 0 to...
8 Monate vor | 0
How to read a vectore in worksapce as a signal in Simulink with variable starting index
I suggest using the MATLAB Function block for the index calculation. You can use the initial index and then compute the new inde...
9 Monate vor | 0
Blocks for HDL Code generation
If you type hdllib on at the MATLAB command line, the Simulink library browser will show you the list of blocks supported for HD...
10 Monate vor | 1
| akzeptiert
Display images on video viewer in simulink in for loop
It would help to have a sample model (a simple one showing the problem will suffice). If you wish to view the intermediate resu...
etwa ein Jahr vor | 0
| akzeptiert
Atan2 block native floating point single HDL generation needs more pipelining
I am glad that using the Complex to Magnitude Angle block worked out for you. Adding that option as an answer in case others run...
etwa ein Jahr vor | 0
| akzeptiert
how to implement this function in fixed point and generate the hdl code for the function?
For HDL, you will need to implement this in a streaming fashion. lease take a look at the FFT Streaming model provided in this e...
etwa ein Jahr vor | 0
Parallelise data coming out of RAM Simulink
What kind of processing do you want to do on the 512-element array? For an HDL implementation, it makes sense to work on a singl...
etwa ein Jahr vor | 0
Sie können auch eine Website aus der folgenden Liste auswählen:
Amerika
- América Latina (Español)
- Canada (English)
- United States (English)
Europa
- Belgium (English)
- Denmark (English)
- Deutschland (Deutsch)
- España (Español)
- Finland (English)
- France (Français)
- Ireland (English)
- Italia (Italiano)
- Luxembourg (English)
- Netherlands (English)
- Norway (English)
- Österreich (Deutsch)
- Portugal (English)
- Sweden (English)
- Switzerland
- United Kingdom (English)
Asien-Pazifik
- Australia (English)
- India (English)
- New Zealand (English)
- 中国
- 日本Japanese (日本語)
- 한국Korean (한국어)