HDL Coder disable Clock Enable output port
9 Ansichten (letzte 30 Tage)
Ältere Kommentare anzeigen
Michael Felger
am 27 Feb. 2019
Beantwortet: Bharath Venkataraman
am 28 Feb. 2019
I can specify the name In HDL Code Generation -> Global Settings -> Ports -> Clock enable output port (default ce_out). But there is no checkbox to disable the output port.
The documentation says "A clock enable output is generated when the design requires one."
What is the condition for "when the design requires one"?
0 Kommentare
Akzeptierte Antwort
Bharath Venkataraman
am 28 Feb. 2019
There is not a separate option - it is assumed that a requirement of a clock enable on the input would mean one is desired on the output.
0 Kommentare
Weitere Antworten (1)
Bharath Venkataraman
am 28 Feb. 2019
You can use the option Minimize Clock Enables to remove the clock enable port. The clock enable typically cannot be removed for multi-rate designs.
HDL Code Generation -> Global Settings -> Ports -> Minimize clock enables (check this box).
Siehe auch
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!