HDL Coder FPGA In The Loop, Error: There is no current hw_target

Using HDL Coder for a matched filter. Everything works up until Verify with FPGA-in-the-Loop.

I have a Zedboard attached with Ethernet and can see the default web page. I DO NOT have a JTAG cable attached; my understanding is that Ethernet works and is faster?

I'm on a Linux box, running Vivado 2020.2 and R2022b

If you can tell me what this error means, I can probably figure it out:

ERROR: [Labtoolstcl 44-469] There is no current hw_target.

Get this error:

### Start loading bitstream "/home/kurt/RxPN/codegen/PNFilterComplex/fil/PNFilterComplex_fixpt_fil/PNFilterComplex_fixpt_fil.bit"

Loading bitstream failed with the following message:

****** Vivado v2020.2 (64-bit)

**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020

**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020

** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source _vivado_program.cmd

# set chain_position 1

# open_hw

WARNING: 'open_hw' is deprecated, please use 'open_hw_manager' instead.

# connect_hw_server -url localhost:3121

INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121

INFO: [Labtools 27-2222] Launching hw_server...

INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2020.2

**** Build date : Nov 18 2020 at 09:50:49

** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042

INFO: [Labtools 27-3417] Launching cs_server...

INFO: [Labtools 27-2221] Launch Output:

******** Xilinx cs_server v2020.2

****** Build date : Nov 03 2020-14:02:56

**** Build number : 2020.2.1604437376

** Copyright 2017-2020 Xilinx, Inc. All Rights Reserved.

# open_hw_target

ERROR: [Labtoolstcl 44-469] There is no current hw_target.

INFO: [Common 17-206] Exiting Vivado at Sat Feb 11 20:55:24 2023...

Error in programXilinxFPGAUsingVivado at 0

Error in filProgramFPGA at 33

Error in run_PNFilterComplex_fixpt_fil at 4

Error in GenMatlabTb>>runSimulation at 0

Error in Manager>>wfa_generateFILTB at 0

Answer 1

[YP]

The message means it failed to program FPGA with JTAG, which should not happen if you are using Ethernet interface.

Please be more specific about your workflow and reproduce steps.

[Dr. W. Kurt Dobson]

I was successful in getting all this to work by installing D2XX drivers which can be found at: https://ftdichip.com/drivers/d2xx-drivers/

Even though Linux could see the JTAG USB device, it could not connect to it.

I'm extremely pleased with the many interactions I've had with MathWorks support. I always get answers to any questions I have