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Simulink Design Verifier Options

Options in Configuration Parameters Dialog Box

You can set options for Simulink® Design Verifier™ analysis in the Configuration Parameters dialog box. To view the options, open the Design Verifier tab. In the Prepare section, from the drop-down menu for the mode settings, click Settings. The Design Verifier pane of the model configuration parameters opens.

By default, options for Simulink Design Verifier do not appear in the Configuration Parameters dialog box. When you open the Design Verifier tab, Simulink Design Verifier associates its default options with the model. After you save the model, you can access options for Simulink Design Verifier directly from the Configuration Parameters dialog box.

See Set Model Configuration Parameters for a Model for more information about working with this interface.

Design Verification Options Objects

You can use the sldvoptions function to specify Simulink Design Verifier options at the command line.

To view in the MATLAB® Command Window the design verification options associated with a Simulink model, use the following syntax:

opts = sldvoptions('model_name');
get(opts)

Command-Line Parameters for Design Verification Options

Use the following parameters to configure the behavior of Simulink Design Verifier. Use the get_param and set_param functions to retrieve and specify values for these parameters programmatically.

For each parameter, the Location column indicates where you can set its value in the Configuration Parameters dialog box. The Values column shows the type of value required, the possible values (separated with a vertical line), and the default value (enclosed in braces).

Parameter

Location

Values

DVAbsoluteTolerance

Set by the Floating point absolute tolerance parameter on the Design Verifier > Test Generation pane.

double {'1.0e-05'}

DVAssertions

Set by the Assertion blocks parameter on the Design Verifier > Property Proving pane.

'EnableAll' | 'DisableAll' | {'UseLocalSettings'}

DVAutomaticStubbing

Set by the Automatic stubbing of unsupported blocks and functions parameter on the Design Verifier pane.

{'on'} | 'off'

DVBlockReplacement

Set by the Apply block replacements parameter on the Design Verifier > Block Replacements pane.

'on' | {'off'}

DVBlockReplacementModelFileName

Set by the File path of the output model parameter on the Design Verifier > Block Replacements pane.

character array {'$ModelName$_replacement'}

DVBlockReplacementRulesList

Set by the List of block replacement rules parameter on the Design Verifier > Block Replacements pane.

character array {'<FactoryDefaultRules>'}

DVCodeAnalysisExtraOptions

Set by the Additional options for code analysis parameter on the Design Verifier pane.

character array {''}

DVCoverageDataFile

Set by the Coverage data file parameter on the Design Verifier > Test Generation pane.

character array {''}

DVCovFilter

Set by the Ignore objectives based on filter parameter on the Design Verifier pane.

'on' | {'off'}

DVCovFilterFileName

Set by the Filter file parameter on the Design Verifier pane.

character array {''}

DVDataFileName

Set by the Data file name parameter on the Design Verifier > Results pane.

character array {'$ModelName$_sldvdata'}

DVDesignMinMaxCheck

Set by the Specified minimum and maximum value violations parameter on the Design Verifier > Design Error Detection pane.

'on' | {'off'}

DVDesignMinMaxConstraints

Set by the Use specified input minimum and maximum values parameter on the Design Verifier pane.

{'on'} | 'off'

DVDetectActiveLogic

Set by Identify active logic on the Design Verifier > Design Error Detection pane.

'on' | {'off'}

DVDetectBlockInputRangeViolations

Set by Specified block input range violations on the Design Verifier > Design Error Detection pane.

'on' | {'off'}

DVDetectDeadLogic

Set by Dead logic (partial) on the Design Verifier > Design Error Detection pane.

'on' | {'off'}

DVDetectDivisionByZero

Set by the Division by zero parameter on the Design Verifier > Design Error Detection pane.

{'on'} | 'off'

DVDetectDSMAccessViolations

Set by the Data store access violations parameter on the Design Verifier > Design Error Detection pane.

'on' | {'off'}

DVDetectInfNaN

Set by the Non-finite and NaN floating-point values parameter on the Design Verifier > Design Error Detection pane.

'on' | {'off'}

DVDetectIntegerOverflow

Set by the Integer overflow parameter on the Design Verifier > Design Error Detection pane.

{'on'} | 'off'

DVDetectOutOfBounds

Set by the Out of bound array access parameter on the Design Verifier > Design Error Detection pane.

{'on'} | 'off'

DVDetectSubnormal

Set by the Subnormal floating-point values parameter on the Design Verifier > Design Error Detection pane.

'on' | {'off'}

DVDisplayReport

Set by the Display report parameter on the Design Verifier > Report pane.

{'on'} | 'off'

DVExtendExistingTests

Set by the Extend existing test cases parameter on the Design Verifier > Test Generation pane.

'on' | {'off'}

DVExistingTestFile

Set by the Data file parameter on the Design Verifier > Test Generation pane.

character array {''}

DVHarnessModelFileName

Set by the Harness model file name parameter on the Design Verifier > Results pane.

character array {'$ModelName$_harness'}

DVHarnessSource

Set by the Harness source parameter on the Design Verifier > Results pane.

{'Signal Builder'} | 'Signal Editor'

DVIgnoreCovSatisfied

Set by the Ignore objectives satisfied in existing coverage data parameter on the Design Verifier > Test Generation pane.

'on' | {'off'}

DVIgnoreExistTestSatisfied

Set by the Ignore objectives satisfied by existing test cases parameter on the Design Verifier > Test Generation pane.

{on'}| 'off'

DVIncludeRelationalBoundary

Set by the Include relational boundary objectives parameter on the Design Verifier > Test Generation pane.

{'on'} | 'off'

DVMakeOutputFilesUnique

Set by the Make output file names unique by adding a suffix check box on the Design Verifier pane.

{'on'} | 'off'

DVMaxProcessTime

Set by the Maximum analysis time parameter on the Design Verifier pane.

double {300}

DVMaxTestCaseSteps

Set by the Maximum test case steps parameter on the Design Verifier > Test Generation pane.

int32 {10000}

DVMaxViolationSteps

Set by the Maximum violation steps parameter on the Design Verifier > Property Proving pane.

int32 {'20'}

DVMode

Set by the Mode parameter on the Design Verifier pane.

{'TestGeneration'} | 'DesignErrorDetection' | 'PropertyProving'

DVModelCoverageObjectives

Set by the Model coverage objectives parameter on the Design Verifier > Test Generation pane.

'None' | 'Decision' | {'ConditionDecision'} | 'MCDC' | 'EnhancedMCDC'

DVModelReferenceHarness

Set by the Reference input model in generated harness parameter on the Design Verifier > Results pane of the Configuration Parameters dialog box.

'on' | {'off'}

DVOutputDir

Set by Output folder on the Design Verifier pane.

character array {'sldv_output/$ModelName$'}

DVParameterConstraints

Set by Constraint column in Parameter Table on the Design Verifier > Parameters pane.

double array {[]}

DVParameterNames

Set by Name column in Parameter Table on the Design Verifier > Parameters pane.

double array {[]}

DVParameterUseInAnalysis

Set by Use column in Parameter Table on the Design Verifier > Parameters pane.

cell array {[]}

DVParameters

Set by Enable parameter configuration on the Design Verifier > Parameters pane.

'on' | {'off'}

DVParametersConfigFileName

Set by Parameter configuration file on the Design Verifier > Parameters pane.

This parameter is disabled when DVParametersUseConfig is set to 'on'.

character array {'sldv_params_template.m'}

DVParametersUseConfig

Set by Use parameter table on the Design Verifier > Parameters pane.

When set to 'on', this parameter disables DVParametersConfigFileName.

'on' | {'off'}

DVProofAssumptions

Set by the Proof assumptions parameter on the Design Verifier > Property Proving pane.

'EnableAll' | 'DisableAll' | {'UseLocalSettings'}

DVProvingStrategy

Set by the Strategy parameter on the Design Verifier > Property Proving pane.

'FindViolation' | {'Prove'} | 'ProveWithViolationDetection'

DVRandomizeNoEffectData

Set by the Randomize data that do not affect the outcome parameter on the Design Verifier > Results pane.

'on' | {'off'}

DVRebuildModelRepresentation

Set by the Rebuild model representation parameter on the Design Verifier pane.

'Always' | {'If change is detected'}

DVReduceRationalApprox

Set by the Run additional analysis to reduce instances of rational approximation parameter on the Design Verifier pane.

{'on'} | 'off'

DVRelativeTolerance

Set by the Floating point relative tolerance parameter on the Design Verifier > Test Generation pane.

double {'0.01'}

DVReportFileName

Set by the Report file name parameter on the Design Verifier > Report pane.

character array {'$ModelName$_report'}

DVReportIncludeGraphics

Set by the Include screen shots of properties parameter on the Design Verifier > Report pane.

'on' | {'off'}

DVReportPDFFormat

Set by the Generate additional report in PDF format parameter on the Design Verifier > Report pane.

'on' | {off'}

DVSaveExpectedOutput

Set by the Include expected output values parameter on the Design Verifier > Results pane.

'on' | {'off'}

DVSaveHarnessModel

Set by the Generate separate harness model after analysis parameter on the Design Verifier > Results pane.

'on' | {off'}

DVSaveReport

Set by the Generate report of the results parameter on the Design Verifier > Report pane.

'on' | {off'}

DVSFcnSupport

Set by the Support S-Functions in the analysis parameter on the Design Verifier pane.

{'on'} | off'

DVSlTestHarnessName

Set by the Test Harness Name parameter on the Design Verifier > Results pane.

character array {'$ModelName$_sldvharness'}

DVSlTestFileName

Set by the Test File Name parameter on the Design Verifier > Results pane.

character array {'$ModelName$_test'}

DVStrictEnhancedMCDC

Set by the Use strict propagation conditions parameter on the Design Verifier > Test Generation pane.

'on' | {'off'}

DVTestConditions

Set by the Test conditions parameter on the Design Verifier > Test Generation pane.

'EnableAll' | 'DisableAll' | {'UseLocalSettings'}

DVTestgenTarget

Set by the Test generation target parameter on the Design Verifier > Test Generation pane.

{'Model'} | 'GenCodeTopModel' | 'GenCodeModelRef'

DVTestObjectives

Set by the Test objectives parameter on the Design Verifier > Test Generation pane.

'EnableAll' | 'DisableAll' | {'UseLocalSettings'}

DVTestSuiteOptimization

Set by the Test suite optimization parameter on the Design Verifier > Test Generation pane.

If you analyze your model by using the Legacy LargeModel (Nonlinear Extended), the software displays a warning message that this option has been removed and suggests that you use Auto instead.

{'Auto'} | 'IndividualObjectives' | 'LongTestcases' | 'LargeModel (Nonlinear Extended)'

DVUseParallel

Set by the Validate test cases or counterexamples with parallel computing parameter on the Design Verifier pane.

'on' | {'off'}

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