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Functions for Component Verification

The Simulink® Design Verifier™ software provides several functions that facilitate the tasks associated with component verification.

FunctionTask
sldvlogsignals

Simulate a Simulink model and log input signals to a Model block in the model. If you modify the test cases in the Signal Builder harness model, use this approach for logging input signals to the harness model itself.

sldvmakeharness

Create a harness model for a component, using logged input signals if specified, or using the default signals.

For more information about harness models, see Simulink Design Verifier Harness Models.

sldvmergeharness

Merge test cases from several harness models into a single harness model.

sldvextract

Extract an atomic subsystem or atomic subchart into a new model.

sldvruntest

Simulate a model, executing the specified test cases to record model coverage and outport values.

sldvruncgvtest

Invoke the Code Generation Verification (CGV) API, and execute the specified test cases on the generated code for the model.

Note

To execute a model in different modes of execution, use the CGV API to verify the numerical equivalence of results. For more information about the CGV API, see Programmatic Code Generation Verification (Embedded Coder).

Component verification functions do not support the following Simulink features:

  • Variable-step solvers for sldvruntest

  • Component interfaces that contain:

    • Variable-size signals

    • Multiword fixed-point data types larger than 128 bits