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Simulink Design Verifier Harness Models

Harness Model Generation

A harness model provides an isolated environment to test design changes. You can create a harness model during Simulink® Design Verifier™ analysis or after the analysis.

The contents of the harness model depends on the value of the Mode parameter, set in the Configuration Parameters dialog box on the Design Verifier pane:

  • Design error detection — The harness model contains the test cases that result in errors during simulation.

  • Test generation — The harness model contains the test cases that achieve test objectives.

  • Property proving — The harness model contains counterexamples that falsify the proof objectives.

By default, the Generate separate harness model after analysis parameter is disabled.

Note

The Simulink Design Verifier software generates a harness model only when the top-level model that you are analyzing contains an Inport block.

Create a Harness Model

To create a harness model before or after the analysis, use these methods:

  • Before the analysis, in the Configuration Parameters dialog box, on the Design Verifier > Results pane, select Generate separate harness model after analysis.

  • After the analysis, in the Simulink Design Verifier Results Summary window, select Create harness model.

Contents of a Harness Model

Simulink Design Verifier software creates a harness model that contains these items:

  • Inputs — The Inputs block is a Signal Builder or Signal Editor block based on the Harness source option set in the Design Verifier > Results pane.

    • Signal Builder: This block contains signals that are comprised of the test cases or counterexamples that Simulink Design Verifier generates. The Signal Builder block contains signals only for input signals that are used in the model. If an input signal has no effect on the output of the model, that signal is not included in the Signal Builder block.

      To open the Signal Builder dialog box and view its signals, double-click the Inputs block. Each signal group represents a unique test case or counterexample. To view the signals associated with a particular test case or counterexample, in the Signal Builder dialog box, select Active Group.

      After Simulink Design Verifier performs test generation analysis on the sldvdemo_cruise_control model with the default options, this Signal Builder block shows the signals for Test Case 7.

      If you select the LongTestcases option of the Test suite optimization parameter, the analysis creates fewer, longer test cases. For example, if you select the LongTestcases option for the sldvdemo_cruise_control model, the analysis produces one long test case instead of nine shorter test cases. This Signal Builder dialog box shows the signals for the long test case. For more information about the Signal Builder dialog box, see Signal Groups.

    • Signal Editor: This block contains scenarios that are comprised of the test cases or counterexamples that Simulink Design Verifier generates. The Signal Editor block contains signals only for input signals that are used in the model. If an input signal has no effect on the output of the model, that signal is not included in the Signal Editor block.

      After Simulink Design Verifier generates harness model, the input MAT-file for the Signal Editor block is saved at the default location <current_folder>\sldv_output\<model_name>\<model_name>_harness_HarnessInputs.mat.

    To open the Signal Editor dialog box and view the scenarios of signal sources, double-click the Inputs block. The Active scenario lists the test cases or counterexamples. To create and edit scenarios, launch the Signal Editor user interface. For more information, see Create and Edit Signal Data.

  • Size-Type — This Subsystem block transmits signals from the Inputs block to the Test Unit block. It verifies that the size and data type of the signals are consistent with the Test Unit block.

  • Test Unit — This Subsystem block contains a copy of the original model that Simulink Design Verifier analyzed.

    If you select the Reference input model in generated harness on the Design Verifier > Results pane, the Test Unit is a Model block that references the model that you are analyzing, not a subsystem.

    If the Test Unit in the harness model is a subsystem, the values of the parameters on the Optimization and Math and Data Types panes might impact the coverage results.

  • Test Case Explanation — This DocBlock block documents the test cases or counterexamples that Simulink Design Verifier generates. To view the description of each test case or counterexample, double-click the Test Case Explanation block. The block lists either the test objectives that each test case achieves or the proof objectives that each counterexample falsifies.

Configuration of the Harness Model

Simulink Design Verifier generates the harness model with these settings.

  • The harness model start time is always 0. If the original model uses a nonzero start time, the software ignores the start time and uses 0 for the simulation start time for test cases and counterexamples.

  • The harness model stop time always equals the stop time of the longest test case in the Inputs block.

  • By default, the software enables coverage analysis and generates a coverage report for the harness models that contain test cases. The coverage reporting is enabled with default options. You can customize these settings by using Specify Coverage Options (Simulink Coverage).

  • By default, if you select Ignore objective based on filter and provide a coverage filter file for the Test Unit, the coverage filter file applies to the harness model. For more information, see Coverage data.

  • The harness model is generated with these Inputs block, regardless of the Harness source that you specify:

    • For models that use the complex type Inport block, a Signal Editor block is used as the harness source.

    • For models that use an array of buses as an Inport block, a Signal Builder block is used as the harness source.

Note

For models that uses both complex type and array of buses as Inport blocks, harness model generation is not supported.

Simulate the Harness Model

The harness model enables you to simulate a copy of your original model by using the test cases or counterexamples that Simulink Design Verifier generates. Using the harness model, you can simulate:

  • A counterexample.

  • A single test case, for which the Simulink Coverage™ software collects and displays model coverage information.

  • All the test cases, for which the Simulink Coverage software collects and displays cumulative model coverage information.

Note

If you analyze a model that is simulated with sample time warnings, when you simulate the harness model, the warnings might be reported as errors, causing the simulation to fail.

Simulate Harness Model by Using the Signal Builder Source Block

To simulate a single test case or counterexample:

  1. In the harness model, double-click the Inputs block.

  2. In the Signal Builder dialog box, select the Active Group with a particular test case or counterexample.

    The Signal Builder dialog box displays the signals that comprise the selected test case or counterexample.

  3. Click the Start simulation button .

    The Simulink software simulates the harness model by using the signals associated with the selected test case or counterexample. When simulating a test case, the Simulink Coverage software collects model coverage information and displays a coverage report.

To simulate all test cases and measure their combined model coverage:

  1. In the harness model, double-click the Inputs block.

  2. In the Signal Builder dialog box, click the Run all button .

    The Simulink software simulates the harness model by using all test cases, while the Simulink Coverage software collects model coverage information and displays a coverage report.

    When you click Run all, the software simulates all the test cases by using the stop time for the harness model. The stop time equals the stop time for the longest test case, so you might accumulate additional coverage when you simulate the shorter test cases.

For more information, see Simulating with Signal Groups.

Simulate Harness Model by Using the Signal Editor Inputs Block

To simulate a single test case or counterexample:

  1. In the harness model, double-click the Inputs block.

  2. In the Signal Editor dialog box, select the Active scenario with a particular test case or counterexample and click OK.

  3. In the Simulink editor, click the Run button.

    The Simulink software simulates the harness model by using the scenario of signal sources associated with the selected test case or counterexample. When simulating a test case, the Simulink Coverage software collects model coverage information and displays a coverage report.

To simulate all the test cases and measure their combined model coverage, use cvsim (Simulink Coverage) or parsim command. For example, see Simulate Harness Model with Signal Editor Inputs Block.

See Also

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