Export Signal Data Using Signal Logging
To capture signal data from a simulation, usually you can use signal logging. Mark the signals that you want to log and enable signal logging for the model. For details, see Configure a Signal for Logging and Enable Signal Logging for a Model.
For a summary of other approaches to capture signal data, see Export Simulation Data.
Signal Logging Workflow
To collect and use signal logging data, perform these tasks.
Log Subsets of Signals
One approach for testing parts of a model as you develop it is to mark a superset of signals for logging and then override signal logging settings to select different subsets of signals for logging. You can use the Signal Logging Selector or a programmatic interface. See Override Signal Logging Settings.
Use this approach to log signals in models that use model referencing. For an example, see Viewing Signals in Model Reference Instances.
Additional Signal Logging Options
With the basic signal logging workflow, you can specify additional options related to the data that signal logging collects and to how that data is displayed. You can:
Specify a name for the signal logging data for a signal. See Specify Signal-Level Logging Name.
Control how much data the simulation generates for a signal. See Limit Data Logged.
Review the signal logging configuration for a model. See View the Signal Logging Configuration.
Specify the samples for export for models with variable-step solvers. See Samples to Export for Variable-Step Solvers.
Signal Logging Limitations
Signal logging does not support:
Signals inside Stateflow® charts for rapid accelerator simulations.
Input signals for Function-Call subsystems, If Action subsystems, or Switch Case Action subsystems.
Input signals for Merge blocks.
Bus signals inside For Each subsystems.
Signals in referenced models inside For Each subsystems when:
The model containing the For Each subsystem simulates in rapid accelerator mode.
The For Each subsystem is inside a referenced model simulated in accelerator mode.
State port signals for Integrator and Discrete-Time Integrator blocks that show the state port.