HF-Signale und Mixed-Signal

Modellieren und Simulation von HF-, SerDes- und Mixed-Signal-Systemen

Mit den folgenden Simulink^®-Produkten können Sie Hochfrequenz-Systeme (HF), SerDes-Systeme (Serialisierer/Deserialisierer) und Mixed-Signal-Systeme mit höherer Geschwindigkeit und Präzision modellieren und simulieren.

RF Blockset ermöglicht es Ihnen, HF-Elemente zu modellieren und HF-Sendeempfänger und -Frontends mit verschiedenen Abstraktionsgraden zu simulieren. Sie können HF-Modelle charakterisieren, um adaptive Architekturen zu modellieren, darunter AGC, DPD-Algorithmen und Beamforming. Mit RF Blockset können Sie zudem die Details der Modellimplementierung verbergen.
SerDes Toolbox ermöglicht es Ihnen, SerDes-Systeme zu modellieren und IBIS-AMI-Modelle für digitale Hochgeschwindigkeits-Verbindungsleitungen zu erstellen. Sie können die Auswirkungen von ISI, Jitter, Rauschen, Einfügedämpfung und Überlagerung beobachten und die Compliance des Kanals mit Industriestandard wie IEEE 802.3, OIF, PCle, USB und DDR5 überprüfen.
Mixed-Signal Blockset ermöglicht Ihnen die Modellierung von ADC-, DAC-, PLL- und SMPS-Systemen. Zudem können Sie Mixed-Signal-ICs überprüfen und analoge Schaltkreisverhalten mit digitalen Modellen kombinieren, um elektronische Systeme detaillierter darzustellen.

Themen

Getting Started with RF Modeling (RF Blockset)
Build a simple RF receiver and perform circuit envelope simulation.
Design SerDes System and Export IBIS-AMI Model (SerDes Toolbox)
Create and analyze a SerDes system, and export an IBIS-AMI model using the SerDes Designer app.
Design and Evaluate Simple PLL Model (Mixed-Signal Blockset)
This example shows how to design a simple phase-locked loop (PLL) using a reference architecture and validate it using PLL Testbench.

Enthaltene Beispiele

Top-Down Design of RF Receiver

Design an RF receiver for a ZigBee-like application using a top-down methodology.

Power Amplifier and DPD Modeling for Dynamic EVM Measurement

Extract a PA model using measured data, verify the quality of the fitting, and simulate the PA model with and without DPD.

Enable Model Protection and Accelerator Modes in RF Blockset Models

Conceal implementation details and enable accelerator modes in your RF Blockset model.

Architectural 112G PAM4 ADC-Based SerDes Model

Model a 112G PAM4 time-interleaved ADC-Based SerDes.

PCIe6 Transmitter/Receiver IBIS-AMI Model

Create IBIS-AMI models for a PCI-Express Generation 6 (PCIe Gen6) transmitter and receiver using the library blocks in SerDes Toolbox™. The IBIS-AMI models generated by this example can be used in Serial Link Designer from Signal Integrity Toolbox™ and conform to the PCIe Gen6 Base-Specification published by the PCI-SIG.

USB4 V2 Transmitter/Receiver IBIS-AMI Model

Implement USB4 V2 (80Gbps PAM3) Transmitter and Receiver architectures with SerDes Designer and generate IBIS-AMI models using the library blocks in SerDes Toolbox™. The generated models conform to the IBIS-AMI and USB4 V2 specifications.

Design and Evaluate Successive Approximation ADC Using Stateflow

Design and evaluate a 12-bit successive approximation register ADC.

Boost Power Train Design Workflow

Design a power supply with a boost power train for a specific operating point, control the output voltage, and perform time-domain simulations.

Digital Phase Locked Loop

Model a digital phase locked loop using the Mixed-Signal Blockset™. In a digital phase locked loop, phase detection is performed by a time to digital converter (TDC), loop filtering is performed by a digital filter, and the oscillator is a digitally controlled oscillator (DCO). This example demonstrates a behavioral model of a TDC, using the BiquadFilter from the DSP System Toolbox™ as the digital loop filter, and using VCOs and DACs from the Mixed-Signal Blockset to model the DCO.