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Test designs in real hardware

Creating an FPGA-in-the-loop link between the simulator and the board enables you to:

  • Verify HDL implementations directly against algorithms in Simulink® or MATLAB®.

  • Apply data and test scenarios from Simulink or MATLAB to the HDL design on the FPGA.

  • Integrate existing HDL code with models under development in Simulink or MATLAB.

Before you can use FPGA-in-the-loop (FIL) simulation, you must download the support package for your board. See Download FPGA Board Support Package. Alternatively, you can manually create custom board definition files for use with FIL simulation. See FPGA Board Customization.

After you download a board support package, select a simulation workflow. See FPGA-in-the-Loop Simulation Workflows. To learn how FIL simulation works, see FPGA-in-the-Loop Simulation.


HDL VerifierGenerate HDL verification artifacts and follow verification workflows from a Simulink subsystem (Since R2020b)
FPGA-in-the-Loop WizardGenerate an FPGA-in-the-loop (FIL) block or System object from existing HDL files
Logic AnalyzerVisualize, measure, and analyze transitions and states over time


hdlverifier.FILSimulation FIL simulation with MATLAB


filProgramFPGALoad programming file onto FPGA
programFPGA Load programming file associated with FILSimulation system object onto FPGA


FIL SimulationSimulate HDL code on FPGA hardware from Simulink



  • FPGA-in-the-Loop Simulation Workflows
    Choose between generating a block or System object™, and decide whether to use the FIL Wizard or HDL Workflow Advisor.
  • FPGA-in-the-Loop Simulation
    FPGA-in-the-loop (FIL) simulation provides the capability to use Simulink or MATLAB software for testing designs in real hardware for any existing HDL code.

FIL Requirements and Preparation

Generate FIL Interface from Legacy Code

Generate FIL System Object from MATLAB Code (requires HDL Coder license)

Generate FIL Block from Simulink Model (requires HDL Coder license)


Troubleshooting FIL

Fixes for common error messages and issues.