hdlverifier.FILSimulation

FIL simulation with MATLAB

Description

The FILSimulation System object™ connects an FPGA execution to a MATLAB® test bench. It does so by applying input signals to and reading output signals from an HDL model running on an FPGA. You can use this object to model a source or sink device by configuring the object with input or output ports only.

To run a simulation consisting of a MATLAB test bench communicating with an FPGA execution:

  1. Customize the hdlverifier.FILSimulation object using FPGA-in-the-Loop Wizard.

  2. Create the object in your design and set its properties.

  3. Call the object with arguments, as if it were a function.

To learn more about how System objects work, see What Are System Objects? (MATLAB).

Creation

To create an hdlverifier.FILSimulation System object, use the FPGA-in-the-Loop Wizard to customize the FILSimulation System object. The output of the FILWizard is a file called toplevel_fil, where toplevel is the name of the top level HDL module. You can then create the System object by assigning it to a local variable.

filobj = toplevel_fil creates the System object customized by the FPGA-in-the-Loop Wizard. toplevel is the name of the top-level module in your HDL code.

You can create the System object and set its properties:

filobj = toplevel_fil('InputSignals', {'/top/in1','/top/in2'}, ...
                           'OutputSignals', {'/top/out1','/top/out2'}, ...
                           'OutputDataTypes', {'double','fixedpoint'}, ...
                           'OutputSigned', [true,false]);
You can also adjust writable properties after creating the System object:
filobj = toplevel_fil;
filobj.OutputDataTypes = char('fixedpoint', 'integer', 'fixedpoint');
filObj.OutputSigned = [false, true, true];

Properties

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Unless otherwise indicated, properties are nontunable, which means you cannot change their values after calling the object. Objects lock when you call them, and the release function unlocks them.

If a property is tunable, you can change its value at any time.

For more information on changing property values, see System Design in MATLAB Using System Objects (MATLAB).

This property is read-only.

Parameters for the connection with the FPGA board, specified as a character vector or string scalar. The vector consists of three parts:

  • Connection type

  • Board IP address

  • Board MAC address (optional)

Example: char('UDP','192.168.0.2','00-0A-35-02-21-8A') specifies a UDP connection to IP address 192.168.0.2, where the board's MAC address is 00-0A-35-02-21-8A.

This property is read-only.

Design under test (DUT) top-level name, specified as a character vector or string scalar.

Example: 'inverter_top'

This property is read-only.

FPGA board name, specified as a character vector or string scalar.

Path to the FPGA programming file, specified as a character vector or string scalar.

Example: 'c:\work\filename'

This property is read-only.

Name of the FPGA chip vendor, specified as 'Xilinx', 'Microsemi', or 'Altera'.

Example: 'Altera'

This property is read-only.

Input widths in bits, specified as an integer or a vector of integers. When this property is an integer, all inputs have the same bit width. When this property is a vector of integers, the vector must be the same size as the number of inputs, where each value specifies a different input width.

Example: 10 – All inputs are ten bits wide.

Example: [12,6,1] – The design has three inputs: One is 12 bits wide, one is 6 bits wide, and one is 1 bit wide.

This property is read-only.

Input paths in the HDL code, specified as a character vector, cell array of character vectors, string scalar, or string array.

Example: '/top/in1'

Example: char('in1','in2')

This property is read-only.

Output widths in bits, specified as an integer or a vector of integers.

If you specify a scalar, the outputs each have the same bit width. If you specify a vector, the vector must be the same size as the number of outputs.

Example: 10 – All outputs are 10 bits wide.

Example: [12,6,1] – The design has three outputs: one is 12 bits wide, one is 6 bits wide, and one is 1 bit wide.

Output data types, specified as a character vector, cell array of character vectors, string scalar, or string array.

If you specify only one data type, all outputs have the same type. Otherwise, specify a cell array of the same size as the number of outputs.

Example: 'integer'

Example: char('integer','fixedpoint','integer')

Downsampling factor and phase of the outputs, specified as a vector of two integers. The first integer specifies the downsampling factor and is positive. The second integer specifies the phase and is either zero or positive but less than the downsampling factor.

Example: [3,1]

Output fraction lengths, specified as an integer or as a vector of integers.

If you only specify a scalar, each output has the same fraction length. Otherwise specify a vector of the same size as the number of outputs.

Example: 10 — All output fraction lengths are 10 bits.

Example: [16,8] — One output fraction length is 16 bits, and the other one has a fraction length of 8 bits.

This property is read-only.

Output port names in the HDL top-level module, specified as a character vector, cell array of character vectors, string scalar, or string array.

Example: 'out1',

Example: char('out1','out2')

Sign of the outputs, specified as false (unsigned), true (signed), or as a logical vector.

If you provide only a scalar, each output has the same sign. Otherwise, you should provide a vector of the same size as the number of outputs.

Example: true

Example: [true, true, false] — Three outputs consisting of a signed value, an unsigned value, and a signed value.

Hardware overclocking factor, specified as an integer.

Example: 3

This property is read-only.

Position of the FPGA in the JTAG scan chain, specified as a positive integer.

Example: 1

Frame size of the source, specified as an integer. This property is relevant only for HDL source blocks, that is, HDL blocks that have no inputs.

Example: 1

Usage

Description

example

[hdloutputs] = filobj([hdlinputs]) connects to the FPGA, writes hdlinputs to the FPGA and reads hdloutputs from the FPGA.

Input Arguments

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Inputs to run on the FPGA, specified as an array of values. The size of the array must much the number of inputs of the module executed on the FPGA.

Example: [RealFft, ImagFft] = fft_obj(3,12); the values 3 and 12 are driven into the FPGA.

Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | logical | Fixed-point

Output Arguments

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Outputs returned from the FPGA, specified as an array of values. The size of the array matches the number of outputs of the module executed on the FPGA.

Example: [RealFft, ImagFft] = fft_obj(real_in,imaginary_in); returns a complex number from the FPGA with two values: RealFft and ImagFft.

Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | logical | Fixed-point

Object Functions

To use an object function, specify the System object as the first input argument. For example, to release system resources of a System object named obj, use this syntax:

release(obj)

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stepRun System object algorithm
releaseRelease resources and allow changes to System object property values and input characteristics
resetReset internal states of System object

Examples

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This example use a MATLAB System object and a FPGA to verify a register transfer level (RTL) design of a Fast Fourier Transform (FFT) of size 8 written in Verilog. The FFT is commonly used in digital signal processing to produce frequency distribution of a signal.

To verify the correctness of this FFT, a MATLAB System object testbench is provided. This testbench generates a periodic sinusoidal input to the HDL design under test (DUT) and plots the Fourier Coefficients in the Complex Plane.

Set FPGA Design Software Environment

Before using FPGA-in-the-Loop, make sure your system environment is set up properly for accessing FPGA design software. You can use the function hdlsetuptoolpath to add ISE or Quartus II to the system path for the current MATLAB session.

For Xilinx FPGA boards, run

>>hdlsetuptoolpath('ToolName', 'Xilinx ISE', 'ToolPath', 'C:\Xilinx\13.1\ISE_DS\ISE\bin\nt64\ise.exe');

This example assumes that the Xilinx ISE executable is C:\Xilinx\13.1\ISE_DS\ISE\bin\nt64\ise.exe. Substitute with your actual executable if it is different.

For Altera boards, run

>>hdlsetuptoolpath('ToolName','Altera Quartus II','ToolPath','C:\altera\11.0\quartus\bin\quartus.exe');

This example assumes that the Altera Quartus II executable is C:\altera\11.0\quartus\bin\quartus.exe. Substitute with your actual executable if it is different.

Copy FFT HDL Files

Copy the HDL files for the FFT example into your local directory

copyFILDemoFiles('fft');

Launch FilWizard

Launch the FIL Wizard prepopulated with the FFT example information. Enter your FPGA board information in the first step, follow every step of the Wizard and generate the FPGA programming file and FIL System object.

filWizard('fft_hdlsrc/fft8_sysobj_fil.mat');

Program FPGA

Program the FPGA with the generated programming file. Before continuing, make sure the FIL Wizard has finished the FPGA programming file generation. Also make sure your FPGA board is turned on and connected properly.

run('fft8_fil/fft8_programFPGA');
### Generating iMPACT command file
### Checking iMPACT tool
### Start loading bitstream "S:\MATLAB\demo\fft8_fil\fft8_fil.bit"
### Loading bitstream "S:\MATLAB\demo\fft8_fil\fft8_fil.bit" completed successfully

Instantiate SineWave System Objects

The following code instantiates the system objects that represent the sine wave generator (F=100Hz, Sampling=1000Hz, complex fix point output).

SinGenerator = dsp.SineWave('Frequency ', 100, ...
                            'Amplitude', 1, ...
                            'Method', 'Table lookup', ...
                            'SampleRate', 1000, ...
                            'OutputDataType', 'Custom', ...
                            'CustomOutputDataType', numerictype([], 10, 9), ...
                            'ComplexOutput',true);

Instantiate the FPGA-in-the-Loop System Object

fft8_fil is a customized FILSimulation System object, which represents the HDL implementation of the FFT running on the FPGA in this simulation system.

Fft = fft8_fil;

Run the Simulation

This example simulates the sine wave generator and the FFT HDL implementation via the FPGA-in-the-Loop System object. This section of the code calls the processing loop to process the data sample-by-sample.

for ii=1:1000
    % Read 1 sample from the sine wave generator
    ComplexSinus = step(SinGenerator);

    % Send/receive 1 sample to/from the HDL FFT on the FPGA
    [RealFft, ImagFft] = step(Fft,real(ComplexSinus),imag(ComplexSinus));

    % Store the FFT sample in a vector
    ComplexFft(ii) = RealFft + ImagFft*1i;
end

Display the Fourier Coefficients

Plot the Fourier Coefficients in the Complex Plane.

% Discard the first 12 samples (initialization of the HDL FFT)
ComplexFft(1:12)=[];

% Display the FFT
plot(ComplexFft,'ro');
title('Fourier Coefficients in the Complex Plane');
xlabel('Real Axis');
ylabel('Imaginary Axis');

% This concludes the "FPGA-in-the-Loop simulation using MATLAB System
% Object" example.

Introduced in R2012b