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Prepare DUT For FIL Interface Generation

Files and Information Required for FIL Generation

For FIL Wizard

Have the following items or information ready:

  • Provide HDL code (either manually written or software generated) for the design you intend to test.

  • Select HDL files and specify the top-level module name.

  • Review port settings and make sure the FIL wizard identified input and output signals and signal sizes as expected.

  • If you are using Simulink®, provide a Simulink model ready to receive the generated FIL block.

Next Steps

For HDL Workflow Advisor

You can generate code and run FIL from any suitable Simulink model.

Next Steps

Apply FIL System Object Requirements

The FIL Process for System Objects

The FIL wizard and HDL Coder™ HDL Workflow Advisor each perform the following actions:

  • Convert HDL code into System object inputs and outputs.

  • Walk you through identifying: FPGA device, source files, I/O ports, and port info.

  • Add logic to the device under test (DUT) to communicate with MATLAB®.

    Generally, this logic is small and has minimal impact on the fit of your design onto the FPGA.

  • Create the programming file and a FIL System object.

Note

If a design does not fit in the device or does not meet timing goals, the software may not create a programming file. In this situation, you may see a warning that the design does not meet the timing goals, but it still generates a programming file, or you may get an error and no programming file. Either change your design, or use a different development board.

When FIL interface generation is complete, you can use the method programFPGA to load the programming file to the FPGA board. You can also use this method to adjust runtime options and signal attributes.

When you are ready to begin, read through the following topics and make sure that your DUT adheres to the rules and guidelines described in each section:

When you are finished with these sections, next go to either System Object Generation with the FIL Wizard or FIL Simulation with HDL Workflow Advisor for MATLAB.

HDL Code Considerations for FIL System Objects

Follow these rules when using legacy or auto-generated HDL code for generating a FIL System object.

CategoryConsiderations
HDL filesAll HDL names must be legal as defined in the VHDL® 1993 standard.
Top-level design
  • The top-level design must be VHDL or Verilog®.

  • The top-level HDL file must contain an entity/module with the same name as the file name.

  • FIL block generation supports both combinatorial and sequential logic. For combinatorial logic, CLK, CLK_ENABLE, and RESET are not required.

Inputs and outputs
  • Input and output ports must be of the following types:

    • std_logic (VHDL)

    • std_logic_vector (VHDL)

    • Reg, wire (Verilog)

  • Vector ports range must be:

    • Descending (e.g. 9 DOWNTO 0, 9:0)

    • Literal. Use of generics (VHDL) or parameters (Verilog) is not supported. (e.g. a DOWNTO b or a:b is not supported)

      Descending TO syntax is not supported

  • For Verilog, ports names must be lowercase. Module name must be lowercase, also.

  • All input and output ports must be included.

  • There must be at least one output port.

Clock
  • Sequential HDL design must have only one clock at the top entity. Clock and reset are required. For combinatorial HDL design, the clock bundle is not required.

  • Name your clock signal clock or clk. If the clock is not named clock or clk, designate which signal is the clock signal in the FIL wizard.

  • Clock port must be 1-bit. For VHDL, it must be of type std_logic.

Reset
  • The HDL design must have a reset to be able to reset the FPGA before simulation.

  • For sequential design, there must be only one reset. Clock and reset are required. For combinatorial HDL design, the clock bundle is not required.

  • Name your reset signal reset or rst. If the reset is not named reset or rst, designate which signal is the reset signal in the FIL wizard.

  • Reset port must be 1-bit. For VHDL, these ports must be of type std_logic.

Clock enable
  • For sequential design, if you choose a clock enable, there must be only one.

  • Clock enable port must be 1-bit. For VHDL, these ports must be of type std_logic.

  • If you have a clock enable, name it one of the following: clock_enable, clock_enb, clock_en, clk_enable, clk_enb, clk_en, ce. If the clock enable is not named one of these names, designate which signal is the clock enable signal in the FIL wizard.

DUT entityAll the ports at DUT level must specify a bit width. Using a variable as the bit width is not allowed.
Clock edgeClock the DUT input and output ports by positive edge. Negative edge is not allowed.
Non-supported data types
  • Bidirectional ports

  • Arrays, record types

Non-supported constructs
  • VHDL configuration statement

  • Verilog include files

  • Macros

  • Escaped names

  • Duplicated port names (Verilog)

FIL-Specific Rules for System Objects

FIL input and output data set limits
  • Total input data size must be less than 1467 bytes. The input data size is the sum of the input bits rounded up to the nearest byte.

  • Output data size must also be less than 1467 bytes. The output data size is the sum of the output bits rounded up to the nearest byte.

Output frame size

Output frame size = Input frame size × OverclockingFactor / OutputDownsample

MATLAB Code Considerations for FIL System Objects

MATLAB compatibilities

HDL Verifier™ FIL simulation supports only the following data types:

  • Integer

  • Logical

  • Fixed point

Apply FIL Block Requirements

The FIL Process for Blocks

The FIL wizard and HDL Coder HDL Workflow Advisor each perform the following actions:

  • Convert HDL code into block signals with timing applied.

  • Walk you through identifying: FPGA device, source files, I/O ports, and port info.

  • Add logic to the device under test (DUT) to communicate with Simulink.

    Generally, this logic is small and has minimal impact on the fit of your design onto the FPGA.

  • Create the programming file and a FIL simulation block.

Note

If a design does not fit in the device or does not meet timing goals, the software may not create a programming file. In this situation, you may see a warning that the design does not meet the timing goals, but it still generates a programming file, or you may get an error and no programming file. Either change your design, or use a different development board.

After FIL interface generation is complete, use the FIL block mask to load the programming file to the FPGA board. You can also adjust runtime options and signal attributes.

When you are ready to begin, read through the following topics and make sure that your DUT adheres to the rules and guidelines described in each section:

When you are finished with these sections, next go to Block Generation with the FIL Wizard or FIL Simulation with HDL Workflow Advisor for Simulink.

HDL Code Considerations for FIL Blocks

Follow these rules when using legacy or auto-generated HDL code for generating a FIL block.

CategoryConsiderations
HDL filesAll HDL names must be legal as defined in the VHDL 1993 standard.
Top-level design
  • The top-level design must be VHDL or Verilog.

  • The top-level HDL file must contain an entity/module with the same name as the file name.

  • FIL block generation supports both combinatorial and sequential logic. For combinatorial logic, CLK, CLK_ENABLE, and RESET are not required.

Inputs and outputs
  • Input and output ports must be of the following types:

    • std_logic (VHDL)

    • std_logic_vector (VHDL)

    • Reg, wire (Verilog)

  • Vector ports range must be:

    • Descending (e.g. 9 DOWNTO 0, 9:0)

    • Literal. Use of generics (VHDL) or parameters (Verilog) is not supported. (e.g. a DOWNTO b or a:b is not supported)

      Descending TO syntax is not supported

  • For Verilog, ports names must be lowercase. Module name must be lowercase, also.

  • All input and output ports must be included.

  • There must be at least one output port.

Clock
  • Sequential HDL design must have only one clock at the top entity. Clock and reset are required. For combinatorial HDL design, the clock bundle is not required.

  • Name your clock signal clock or clk. If the clock is not named clock or clk, designate which signal is the clock signal in the FIL wizard.

  • Clock port must be 1-bit. For VHDL, it must be of type std_logic.

Reset
  • The HDL design must have a reset to be able to reset the FPGA before simulation.

  • For sequential design, there must be only one reset. Clock and reset are required. For combinatorial HDL design, the clock bundle is not required.

  • Name your reset signal reset or rst. If the reset is not named reset or rst, designate which signal is the reset signal in the FIL wizard.

  • Reset port must be 1-bit. For VHDL, these ports must be of type std_logic.

Clock enable
  • For sequential design, if you choose a clock enable, there must be only one.

  • Clock enable port must be 1-bit. For VHDL, these ports must be of type std_logic.

  • If you have a clock enable, name it one of the following: clock_enable, clock_enb, clock_en, clk_enable, clk_enb, clk_en, ce. If the clock enable is not named one of these names, designate which signal is the clock enable signal in the FIL wizard.

DUT entityAll the ports at DUT level must specify a bit width. Using a variable as the bit width is not allowed.
Clock edgeClock the DUT input and output ports by positive edge. Negative edge is not allowed.
Non-supported data types
  • Bidirectional ports

  • Arrays, record types

Non-supported constructs
  • VHDL configuration statement

  • Verilog include files

  • Macros

  • Escaped names

  • Duplicated port names (Verilog)

Simulink Model Considerations for FIL Blocks

Follow these rules for integrating the FIL block into your Simulink model.

CategoryConsiderations
General model rules
  • Use Single tasking solver mode (set with Configuration Parameters). HDL Verifier FIL does not support multitasking solver mode.

  • Choose discrete, fixed-step solvers or variable-step solvers. HDL Verifier FIL supports both types of solvers.

Incompatibilities with Simulink

HDL Verifier FIL simulation currently does not support the following:

  • Instantiation of the FIL block in a triggered subsystem

  • Instantiation of the FIL block in an asynchronous function-call subsystem

  • A continuous sample time

  • A nonzero sample time offset

Initialization

RAM Initialization: Simulink starts from time 0 every time, which means the RAM in a Simulink model is initialized to zero for each run. However, this assumption is not true in hardware. RAM in the FPGA holds its value from the end of one simulation to the start of the next. If you have RAM in your design, the first simulation matches Simulink, but subsequent runs may not match. The workaround is to reload the FPGA bitstream before rerunning the simulation. To reload the bitstream, click the Load on the FIL block mask.

FIL-Specific Rules for Blocks

FIL block settings rules
  • The input frame size must be an integer multiple of the output frame size.

  • All signals must be of the same bit-width as their corresponding port in the hardware.

  • In frame mode, all inputs must have the same frame size and all outputs must have the same frame size (but possibly different from the inputs).

  • When processing as frames, all input signals must have the same sample times and all output signals must have the same sample times. The output sample time can be different from the input sample time.

  • When processing as samples, only scalars are supported. When processing as frames, only column vectors (N-by-1) are supported.

  • Supported data types are built-in data types and fixed-point data types.

  • Split complex signals into real and imaginary signals. FIL simulation does not support complex signals.

  • The output frame size must be less than the input frame size. This requirement ensures that the output frame has enough data to drive a value at time 0. You can avoid this error by either decreasing the output frame size or sample time, or increasing the input frame size or sample time.

FIL byte size limit
  • Total input data size must be less than 1467 bytes. The input data size is the sum of the input bits rounded up to the nearest byte.

  • Output data size must also be less than 1467 bytes. The output data size is the sum of the output bits rounded up to the nearest byte.