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Mixed Model Design by Using HDL Coder Native Floating Point and Intel Hard Floating Point

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This example shows how to create a model design that consists of HDL Coder™ native floating point (NFP) and Intel® hard floating point (HFP). Using the NFP and HFP blocks together in a mixed design offers better FPGA resource utilizations. For complex models, this mixed design allows you to have bigger design into the FPGA fabric.

Generate HDL Code for Model with NFP Library

1. Set the tool path.

hdlsetuptoolpath('ToolName', 'Intel Quartus Pro', 'ToolPath', 'C:\intelFPGA\21.3\Windows\quartus\bin64\qpro.exe')

2. Open the Simulink® model hdlcoder_adder_nfp. The model consists of two adders. Set the input data type to single. 

open_system('hdlcoder_adder_nfp');

nfp_simulinkmodel.png

3. Open Configuration Parameters dialog box, set Synthesis Tool to Intel Quartus Pro and select a family and device.

nfpModelSettings.png

4. On the Floating Point pane, Set Floating Point IP Library to Native Floating Point .

nfpModelSettings2.png

5. Generate HDL Code for the subsystem.

This figure shows the HDL code generation for the Simulink model in the MATLAB® Command Window.

makehdl_nfp.jpg

6. Generate the test bench for the Simulink model.

This figure shows the HDL test bench generation for the hdlcoder_adder_nfp model. The figure shows the generated HDL files and DO files for compiling and simulating the design.

makehdltb_nfp.jpg

7. The DUT_compile.do file contains these commands for compiling the HDL files which are generated during makehdl( ).

  • vlib work

  • vmap -c

  • vcom DUT_pkg.vhd

  • vcom nfp_add_single.vhd

  • vcom DUT.vhd

8. The DUT_tb_compile.do file contains these commands for compiling the HDL files which are generated during makehdltb( ).

  • vlib work

  • vmap -c

  • vcom DUT_pkg.vhd

  • vcom nfp_add_single.vhd

  • vcom DUT.vhd

  • vcom DUT_tb_pkg.vhd

  • vcom DUT_tb.vhd

9. The DUT_tb_sim.do file contains these commands for simulation using ModelSim® software.

  • onbreak resume

  • onerror resume

  • vsim -voptargs=+acc work.DUT_tb

  • add wave sim:/DUT_tb/u_DUT/clk

  • add wave sim:/DUT_tb/u_DUT/reset

  • add wave sim:/DUT_tb/u_DUT/clk_enable

  • add wave sim:/DUT_tb/u_DUT/In1

  • add wave sim:/DUT_tb/u_DUT/In2

  • add wave sim:/DUT_tb/u_DUT/In4

  • add wave sim:/DUT_tb/u_DUT/ce_out

  • add wave sim:/DUT_tb/u_DUT/Out1

  • add wave sim:/DUT_tb/Out1_ref

  • run -all

Generate HDL Code for Model with Intel HFP Library

10. Open the Simulink model hdlcoder_adder_hfp which contains single adder. Set the input data type to single. 

open_system('hdlcoder_adder_hfp');

hfp_simulinkmodel.png

11. Open Configuration Parameters, set Synthesis Tool to Intel Quartus Pro and Floating Point IP Library to ALTERA FP FUNCTIONS in the Floating Point pane.

hfpModelSettings.png

12. To generate HDL code with HFP, select the DUT inside the model and run the makehdl(gcb) command for this model.

This figure shows the generated HDL code.

hfp_makehdl.JPG

13. Generate the test bench for the Simulink model.

This figure shows the HDL test bench generation using makehdltb( ) for the Simulink model.

hfp_makehdltb.JPG

14. The DUT_compile.do file contains these commands for compiling the HDL files which are generated during makehdl( ).

  • vlib work

  • vmap -c

  • vmap -c -modelsimini E:/share/apps/HDLTools/Altera/20.1.1-mw-0/Linux/quartus/bin64/simlibs/modelsim.ini

  • vlib altera_fp_functions_1911

  • vcom -work altera_fp_functions_1911 Altera\Stratix_10\1SX280LN2F43E1VG\F100\synth\alterafpf_add_single\altera_fp_functions_1911\dspba_library_package.vhd

  • vcom -work altera_fp_functions_1911 Altera\Stratix_10\1SX280LN2F43E1VG\F100\synth\alterafpf_add_single\altera_fp_functions_1911\dspba_library.vhd

  • vcom -work altera_fp_functions_1911 Altera\Stratix_10\1SX280LN2F43E1VG\F100\synth\alterafpf_add_single\altera_fp_functions_1911\alterafpf_add_single_altera_fp_functions_1911_sbsskbq.vhd

  • vlib work

  • vcom Altera/Stratix_10/1SX280LN2F43E1VG/F100/synth/alterafpf_add_single.vhd

  • vcom DUT.vhd

15. The DUT_tb_compile.do file contains these commands for compiling the HDL files which are generated during makehdltb( ).

  • vlib work

  • vmap -c

  • vmap -c -modelsimini E:/share/apps/HDLTools/Altera/20.1.1-mw-0/Linux/quartus/bin64/simlibs/modelsim.ini

  • vlib altera_fp_functions_1911

  • vcom -work altera_fp_functions_1911 Altera\Stratix_10\1SX280LN2F43E1VG\F100\synth\alterafpf_add_single\altera_fp_functions_1911\dspba_library_package.vhd

  • vcom -work altera_fp_functions_1911 Altera\Stratix_10\1SX280LN2F43E1VG\F100\synth\alterafpf_add_single\altera_fp_functions_1911\dspba_library.vhd

  • vcom -work altera_fp_functions_1911 Altera\Stratix_10\1SX280LN2F43E1VG\F100\synth\alterafpf_add_single\altera_fp_functions_1911\alterafpf_add_single_altera_fp_functions_1911_sbsskbq.vhd

  • vlib work

  • vcom Altera/Stratix_10/1SX280LN2F43E1VG/F100/synth/alterafpf_add_single.vhd

  • vcom DUT.vhd

  • vcom DUT_tb_pkg.vhd

  • vcom DUT_tb.vhd

16. The DUT_tb_sim.do file contains these commands for the ModelSim simulation.

  • onbreak resume

  • onerror resume

  • vsim -t 1ps -L lpm -L altera_mf -voptargs=+acc work.DUT_tb

  • add wave sim:/DUT_tb/u_DUT/clk

  • add wave sim:/DUT_tb/u_DUT/reset

  • add wave sim:/DUT_tb/u_DUT/clk_enable

  • add wave sim:/DUT_tb/u_DUT/In1

  • add wave sim:/DUT_tb/u_DUT/In4

  • add wave sim:/DUT_tb/u_DUT/ce_out

  • add wave sim:/DUT_tb/u_DUT/Out1

  • add wave sim:/DUT_tb/Out1_ref

  • run -all

Manually Integrate and Merge Files

1. Manually integrate the top module files that you generated in steps 5 and 12. Replace the second NFP adder with the HFP adder, as this figure shows. Adjust the latency difference in the top module and copy all the required supporting HDL files from the HFP folder to NFP folder.

manualIntegration1.png

2. Manually combine the DUT_compile.do files.

  • vlib work

  • vmap -c

  • vmap -c -modelsimini /mathworks/devel/src/commercial/HDLTools/Altera/QuartusPro_SimLibs/20.2_21.2/modelsim.ini

  • vlib altera_fp_functions_191

  • vcom -work altera_fp_functions_191 Altera/Stratix_10/10AS016C3U19E2LG/F200/synth/alterafpf_add_single/altera_fp_functions_191/dspba_library_package.vhd

  • vcom -work altera_fp_functions_191 Altera/Stratix_10/10AS016C3U19E2LG/F200/synth/alterafpf_add_single/altera_fp_functions_191/dspba_library.vhd

  • vcom -work altera_fp_functions_191 Altera/Stratix_10/10AS016C3U19E2LG/F200/synth/alterafpf_add_single/altera_fp_functions_191/alterafpf_add_single_altera_fp_functions_191_nmdr4oq.vhd

  • vlib work

  • vcom DUT_pkg.vhd

  • vcom nfp_add_single.vhd

  • vcom Altera/Stratix_10/10AS016C3U19E2LG/F200/synth/alterafpf_add_single.vhd

  • vcom DUT.vhd

3. Manually combine the DUT_tb_compile.do files.

  • vlib work

  • vmap -c

  • vmap -c -modelsimini /mathworks/devel/src/commercial/HDLTools/Altera/QuartusPro_SimLibs/20.2_21.2/modelsim.ini

  • vlib altera_fp_functions_191

  • vcom -work altera_fp_functions_191 Altera/Stratix_10/10AS016C3U19E2LG/F200/synth/alterafpf_add_single/altera_fp_functions_191/dspba_library_package.vhd

  • vcom -work altera_fp_functions_191 Altera/Stratix_10/10AS016C3U19E2LG/F200/synth/alterafpf_add_single/altera_fp_functions_191/dspba_library.vhd

  • vcom -work altera_fp_functions_191 Altera/Stratix_10/10AS016C3U19E2LG/F200/synth/alterafpf_add_single/altera_fp_functions_191/alterafpf_add_single_altera_fp_functions_191_nmdr4oq.vhd

  • vlib work

  • vcom DUT_pkg.vhd

  • vcom nfp_add_single.vhd

  • vcom Altera/Stratix_10/10AS016C3U19E2LG/F200/synth/alterafpf_add_single.vhd

  • vcom DUT.vhd

  • vcom DUT_tb_pkg.vhd

  • vcom DUT_tb.vhd

4. Manually combine the DUT_tb_sim.do files.

  • onbreak resume

  • onerror resume

  • vsim -t 1ps -L lpm -L altera_mf -voptargs=+acc work.DUT_tb

  • add wave sim:/DUT_tb/u_DUT/clk

  • add wave sim:/DUT_tb/u_DUT/reset

  • add wave sim:/DUT_tb/u_DUT/clk_enable

  • add wave sim:/DUT_tb/u_DUT/In1

  • add wave sim:/DUT_tb/u_DUT/In2

  • add wave sim:/DUT_tb/u_DUT/In3

  • add wave sim:/DUT_tb/u_DUT/ce_out

  • add wave sim:/DUT_tb/u_DUT/Out1

  • add wave sim:/DUT_tb/Out1_ref

  • run -all

Verify Functionality by Using ModelSim Simulation

Open ModelSim and navigate to the folder containing the DO files.

Run the DO files in this order:

  • do DUT_compile.do

  • do DUT_tb_compile.do

  • do DUT_tb_sim.do

This figure shows the ModelSim simulation with the a message at the end of the log to indicate that the tests passed.

modelsimSimulation.JPG

Design Synthesis in Intel Quartus Pro

To perform design synthesis of the mixed NFP and HFP design in Intel Quartus Pro software, follow these steps:

1. Open Intel Quartus Pro and create a project.

2. Add all the generated HDL files in the Quartus project, including the NFP top module DUT and all the other supporting files.

3. Set NFP DUT as top module in the Quartus project.

4. Perform design synthesis by following the Intel Quartus Pro workflow.

This figure shows the complete Quartus project which has the combined NFP and HFP files.

quartusProProject.jpg

Summary

This example shows how to combine the HDL Coder native floating point and Intel hard floating point components. You test the functionality of the mixed design in simulation using ModelSim. You can also generate the bitstream for your mixed design using Intel Quartus Pro software and verify the functionality on the hardware board.

See Also