Processor-in-the-Loop-Simulation
Eine Prozessor-in-the-Loop-Simulation (PIL) querübersetzt generierten Quellcode, lädt daraufhin Objektcode herunter und führt diesen auf Ihrer Zielhardware aus. Durch Vergleich der normalen Ergebnisse und der PIL-Simulationsergebnisse können Sie die numerische Äquivalenz Ihres Modells und des generierten Codes testen. Während einer PIL-Simulation können Sie die Codeabdeckung und die Ausführungszeitmetriken für den generierten Code erfassen.
Eine PIL-Simulation erfordert eine Konnektivitätskonfiguration.
Apps
| SIL/PIL Manager | Verify generated code |
Namespaces
target | Manage target hardware and build tool information |
Klassen
Objekte
Funktionen
Themen
- SIL and PIL Simulations
An overview of software-in-the-loop (SIL) and processor-in-the-loop simulations (PIL).
- Choose a SIL or PIL Approach
Test code generated from top models, referenced models, and subsystems.
- Create PIL Target Connectivity Configuration for Simulink
Customize PIL simulation for your target environment.
- Host-Target Communication for Simulink PIL Simulation
Use the
rtiostreamAPI for communication between your development computer and target hardware during a PIL simulation. - Specify Hardware Timer for Simulink
Specify a hardware timer using the Code Replacement Tool.
- Set Up PIL Connectivity by Using Target Framework
Provide PIL connectivity between Simulink® and the target hardware.
- Custom Toolchain Directives Required for Code Coverage and Execution Profiling
Specify compiler directives for building PIL application that supports code coverage analysis and execution profiling.
- Configure and Run PIL Simulation
Set up and run top-model PIL and Model block PIL simulations.
- Unit Test Subsystem Code with SIL/PIL Manager
Perform unit testing on atomic subsystem by using SIL/PIL Manager.
- SIL/PIL Manager Verification Workflow
A simplified workflow for verifying generated code.
- PIL Simulation Sequence
How a PIL simulation proceeds.
- Simulation Mode Override Behavior in Model Reference Hierarchy
How the simulation mode of the top model or parent model determines the simulation behavior of a model hierarchy.
- Field-Oriented Control of Permanent Magnet Synchronous Machine
Simulate motor control system, generate controller code, and use PIL simulation to test numerical equivalence and profile code execution times.
- Security for PIL Simulations
Security measures for PIL simulations.
- SIL and PIL Limitations
Modeling and code generation features that are not supported or partially supported by SIL and PIL simulations.
Fehlersuche
Debug Generated Code During SIL or PIL Simulation
Use a debugger to understand the behavior of generated code.
View SIL and PIL Files in Code Generation Report
Produce a code generation report and static code metrics that cover SIL and PIL files.
Verification of Code Generation Assumptions
The SIL or PIL simulation checks code generation assumptions.
Enthaltene Beispiele
Test Generated Code with SIL and PIL Simulations
Use software-in-the-loop (SIL) and processor-in-the-loop (PIL) simulations to test numerical equivalence between model components and generated code.
Configure Processor-In-The-Loop (PIL) for a Custom Target
Create target connectivity configuration and run PIL simulation.
Create a Target Communication Channel for Processor-in-the-Loop (PIL) Simulation
Use rtiostream interface to provide a communication channel
for PIL simulations.
