M-PSK Modulator Baseband

Modulate using M-ary phase shift keying

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Libraries:
Communications Toolbox / Modulation / Digital Baseband Modulation / PM
Communications Toolbox HDL Support / Modulation / PM

Description

The M-PSK Modulator Baseband block modulates an input signal using M-ary phase shift keying (PSK) and returns a complex baseband output. The modulation order, M, which is equivalent to the number of points in the signal constellation, is determined by the M-ary number parameter. The block accepts scalar or column vector input signals.

Examples

Modulate and Demodulate 8-PSK Signal

Use the Open model button to open the doc_8psk_model model. The model generates an 8-PSK signal, applies white noise, displays the resulting constellation diagram, and computes the error statistics.

Open Model

Ports

Input

Port_1 — Input signal

scalar | vector

Specify the input signal as an integer scalar, integer vector, or binary vector.

• When Input type is Integer, specify the input signal elements as integers from 0 to M – 1.

• When Input type is Bit, specify the input signal as a binary vector in which the number of elements is an integer multiple of the bits per symbol. The bits per symbol is equal to log₂(M).

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean

Output

Port_1 — Output signal

scalar | vector

Output signal, returned as a complex scalar or vector. The output is the complex baseband representation of the PSK-modulated signal.

Data Types: single | double | fixed point

Parameters

M-ary number — Modulation order of the PSK constellation

8 (default) | scalar

Specify the modulation order as a positive integer power of two.

Example: 2 | 16

Input type — Type of input signal

Integer (default) | Bit

Specify the elements of the input signal as integers or bits. If Input type is Bit, the number of samples per frame must be an integer multiple of the number of bits per symbol. The number of bits per symbol is log₂(M).

Constellation ordering — Symbol mapping

Gray (default) | Binary | User-defined

Specify how the integer or group of log₂(M) bits is mapped to the corresponding symbol.

• When Constellation ordering is set to Gray, the input signal is mapped to the output symbols using a Gray-encoded signal constellation.

• When Constellation ordering is set to Binary, the modulated symbol is exp(jϕ+j2πm/M), where ϕ is the phase offset in radians, m is the integer input such that 0 ≤ m ≤ M – 1, and M is the modulation order.

• When Constellation ordering is User-defined, specify a vector of size M, which has unique integer values in the range [0, M–1]. The first element of this vector corresponds to the constellation point having an value of e^jϕ with subsequent elements running counterclockwise.

Example: [0 3 2 1]

Constellation mapping — User-defined symbol mapping

[0:7] (default) | vector

Specify the order in which input integers are mapped to output integers. The parameter is available when Constellation ordering is User-defined, and must be a row or column vector of size M having unique integer values in the range [0, M – 1].

The first element of this vector corresponds to the constellation point at 0 + Phase offset angle, with subsequent elements running counterclockwise. The last element corresponds to the -2π/M + Phase offset constellation point.

Phase offset (rad) — Phase offset in radians

pi/8 (default) | scalar

Specify, in radians, the phase offset of the initial constellation as a real scalar.

Example: pi/4

Output data type — Output data type

double (default) | single | Inherit via back propagation | fixdt(1,16) | fixdt(1,16,0) | <data type expression>

Specify the data type of the modulated output signal. Set this parameter to one of the fixed point options or <data type expression> to enable parameters in which you specify additional details. Set this parameter to Inherit via back propagation, to match the output data type and scaling to the following block in the model.

Block Characteristics

Data Types	Boolean | double | fixed pointa, b | integer | single
Multidimensional Signals	no
Variable-Size Signals	yes
a ufix(1) at the input if ''input type'' is set to ''bit''. ufix(ceil(log2(M))) at input if ''input type'' is set to ''integer'' for M-ary modulation. b Fixed-point outputs must be signed.

More About

Constellation Visualization

Click View Constellation on the block mask to visualize a signal constellation for the specified block parameters. Parameter settings must be applied before viewing a constellation. For more information, see View Constellation of Modulator Block.

Algorithms

For binary-encoding, the output baseband signal maps input bits or integers to complex symbols according to:

$$s_n(t)=\exp \left(j\pi \left(\frac{2n+1}{M}\right)\right);n\in \{0,1,\dots ,M-1\}.$$

When the input is configured for bits, groups of log₂(M) bits represent the complex symbols for the configured symbol mapping. The mapping can be binary encoded, Gray encoded, or custom encoded.

Gray coding has the advantage that only one bit changes between adjacent constellation points, which results in better bit error rate performance. This table shows the mapping between the input and output symbols for 8-PSK modulation with Gray coding.

Input	Output
0	0 (000)
1	1 (001)
2	3 (011)
3	2 (010)
4	6 (110)
5	7 (111)
6	5 (101)
7	4 (100)

This constellation diagram shows the corresponding symbols and their binary values.

References

[1] Proakis, John G. Digital Communications. 4th ed. New York: McGraw Hill, 2001.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Version History

Introduced before R2006a