Xilinx Deployment | Designing a Datapath from an FPGA to a Processor with SoC Blockset
From the series: Designing a Datapath from an FPGA to a Processor with SoC Blockset
This video is part of a series that demonstrates a systematic approach to designing the datapath between the hardware logic of an FPGA and an embedded processor using SoC Blockset™.
In this video, you will see how SoC Blockset can be used to deploy hardware/software applications to a Xilinx Zynq®-7000 SoC ZC706 Evaluation Kit. The SoC Builder tool serves as a cockpit that automates all the tasks necessary to perform C and HDL code generation, to drive Xilinx Vivado®, and to program the Zynq-7000 SoC device.
Once the ZC706 is programmed, the hardware/software application is tested to verify correct operation.
Published: 3 Sep 2019
In this video, we will show how to take a hardware/software application that was built in Simulink with SoC Blockset and deploy it to a Xilinx ZC706 development board. In this example, the application samples an audio signal and classifies it as either a low- or high-frequency signal.
In the previous video, we showed how to use SoC Blockset to model a DDR memory that buffers data being passed from the FPGA to the processor. Other blocks from SoC Blockset were used to represent registers, DIP switches, and LEDs. We used simulation to try different design parameters and showed that the application would meet latency and other requirements.
With simulations completed, the next step is to deploy the application to the Xilinx ZC706 board to test it.
To get started, we set up our session to point to Xilinx Vivado for synthesis and implementation. Then we use the Add-On Explorer to check the SoC Blockset hardware support package has been installed. Here’s the SoC Blockset Support Package for Xilinx right up on top.
Then we’ll set up the board we’ll be using. The support package walks us through the process of creating the image for the SD card for the ZC706. It takes into account how our host computer is networked to the development board, and then writes the necessary firmware to an SD card inserted in the host computer. The support package installer gives instructions, such as which cables need to be plugged in, and verifies the configuration of the Xilinx board.
We then insert the SD card into the slot on the board and power it up. The Xilinx support package tests the board configuration, and once that’s done, we’re ready to go.
Note that this video is based on this example that comes with SoC Blockset. To load the model, just scroll down through the example, and click on soc_hwsw_stream_top to bring up the model.
Notice that the mask on the FPGA portion is labeled “Frame-based processing.” We use frame-based processing to make the simulation of this application run faster. Look under the mask and you can see that the model can be set up for sample-based processing. I’ll switch it over to sample-based processing to generate the application.
Next, I’ll launch SoC Builder. SoC Builder is a tool within SoC Blockset that you can use to deploy applications to Xilinx FPGA, Zynq, and Zynq UltraScale+ boards. Think of SoC Builder as a cockpit that drives MathWorks code generators and Xilinx Vivado. It streamlines the tasks needed to build and run complete hardware/software applications.
There are four steps within SoC Builder: prepare, validate, build, and run.
The Memory Mapper displays the memory map for memory channels and IP cores, including the FPGA algorithm wrapper and the Xilinx AXI Performance Monitor.
In the next screen we set the project folder, and in the following screen we choose which action to perform. We’re going to build the application, then load and run it, but another option would be to set up external mode, which is useful for other sorts of testing.
Now we’re in the validate stage. SoC Builder checks for the correct MathWorks products and compatible Xilinx software, then compiles the model. We’ll speed these actions up from here on out for the purposes of this video.
In the build stage, SoC Builder builds the software application using Embedded Coder and displays it as a report, as shown here. It then generates the IP core for the FPGA algorithm and the test source using HDL Coder, creates the Vivado project, and launches Vivado in an external shell. Vivado can take 30 minutes to generate the programming file, so for your convenience the SoC Blockset support package for Xilinx contains the bitstream for various boards, including the ZC706.
To use this bitstream, copy it from the support package installation directory by scrolling down to the “Implement and Run on Hardware” section of the example, select the copyfile command, and paste it into your MATLAB session like this.
This brings us to SoC Builder’s run phase. Here we enter the IP address of the board and ping the board to test the communication with my desktop computer.
Once that checks out, we can load the bitstream and the executable for the Zynq SoC and run.
Here’s our ZC706 board that’s been programmed with the application. At the top is the switch that’s used to toggle between generating low- and high-frequency sources. Down here is a bank of four LEDs. When the top LED is lit, that indicates the application has identified a low-frequency signal, and the LED below that indicates a high-frequency signal has been detected.
We flick the switch for a high-frequency source, and can see the LEDs update accordingly. Then we can continue to toggle the switch and see the LEDs change as the application classifies the input signal.
This demonstrates how to deploy an application to a Xilinx ZC706 development board with SoC Builder.
The ZC706 is just one of the boards included in the SoC Blockset support package for Xilinx. Here’s a list of all the supported boards.
If your board isn’t on this list, or if you are using a custom board using Xilinx FPGAs or SoCs, on the left is a list of the devices for which MathWorks offers custom board support.
For more information about SoC Blockset and how it can help you design for SoC hardware and software architectures, visit mathworks.com/soc.
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