Simulink Design Verifier

 

Simulink Design Verifier

Identifizieren von Design-Fehlern, Nachweisen der Einhaltung von Anforderungen und Generieren von Tests

Detect Run-Time and Diagnostic Errors

Before you run simulations, you can detect run-time and modeling errors, including integer overflow, division by zero, array out of bounds, subnormal values, and floating-point errors as well as data validity errors.

Find Dead Logic

Find objects in your model that cannot be activated during simulation and execution of generated code.

Analyze Missing Test Coverage

Augment and extend existing manually created test cases to address incomplete model coverage.

Verify Formal Safety Requirements

Verify that your design behaves according to formally defined safety requirements that you express using MATLAB®, Simulink, and Stateflow.

Generate Tests for Code Coverage

Generate test cases to increase coverage of generated code and C/C++ code called from Simulink® blocks and in Stateflow® charts.

Create Requirements-Based Test Cases

Generate test cases from models of system requirements.

Simplify Models for Deployment

After you have fully validated your master variants model, use Variant Reducer to generate a reduced model for a subset of valid configurations. All related files and variable dependencies are also reduced. The reduced artifacts are packaged in a separate folder to enable easy deployment and to share with customers and partners.

“By enabling us to analyze requirements quickly, reuse designs from previous products, and eliminate manual coding errors, Model-Based Design has reduced development times and enabled us to shorten schedules to meet the needs of our customers.”

MyoungSuk Ko, LS Automotive