How to generate Verilog code from Deep Learning Network in MATLAB?
Ältere Kommentare anzeigen
I have trained a Deep Learning Network in MATLAb, now I have to genearte a Verilog code for the same. I went through Deep Learning HDL Toolbox, there I found the methods to deploy the network on FPGA but did not get any method to generate a Verilog code. Please help.
1 Kommentar
Giusy Giulia Tuccari
am 18 Mär. 2022
Did you find any solution?
Akzeptierte Antwort
Weitere Antworten (0)
Kategorien
Mehr zu Deep Learning Processor Customization and IP Generation finden Sie in Hilfe-Center und File Exchange
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!