HDL Coder: PN Sequence Generator block fails path balancing, how to work around this?

2012a. When generating HDL code with HDL coder, it fails path balancing when using the PN sequence generator block. It says this block does not support delay balancing. Is there a workaround for this?

When path balancing fails, the simulink model functionality no longer matches the generated VHDL code. This is catastrophic, as the model then no longer matches the implementation so behaviour in the lab does not match the simulation.

Also, the validation model generation fails as a result of path balancing failing.

What is the recommended workaround for this?

Cheers Andrew

Answer 1

[Kiran Kintali]

hi andrew,

can you share the model which reproduces the issue? thanks.

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