Can I generate HDL Code for models with Xilinx System Generator blocks?
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Does HDL Coder support code generation for models including Xilinx System Generator for DSP blocks?
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Kiran Kintali
am 20 Apr. 2020
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If you have access to R2018a can you try to reproduce the issue in that release? We suspect this is already resolved in 18a release.
Thanks.
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Kiran Kintali
am 21 Apr. 2020
ok, let us know. Thanks
Kiran Kintali
am 20 Apr. 2020
While running the simulation using the TCL script generated by HDL Coder, HDL Coder generates SysGen_with_HDL_Coder_CustomTCL_run.tcl script that is using a Vivado simulation command, launch_modelsim.
The TCL command “launch_modelsim” was supported in older versions of Vivado. Vivado 2017.1 supports following commands to use ModelSim simulator.
set_property target_simulator "ModelSim" [current_project]
launch_simulation -mode "post-synthesis" -type "functional"
In the example above, the options -mode “post_synthesis” and –type “functional” are just for example and should be replaced with an appropriate options.
This issue should be resolved in 18a and older releases. Please confirm.
Thanks
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