Communication from processor (PS) to the FPGA (PL) via AXI4-lite

We are using a Zynq SoC FPGA from Xilinx and want to establish a communication from the processor (PS) to the FPGA (PL) via AXI4-Lite. On our processor a linux-based operating system is running and we are using UIOs to access the AXI4-Lite registers of different IP cores. Therefore, we add our IP core in the device tree as followed:

ip_core@43c00000 {

compatible = "custom_ip,generic-uio,ui_pdrv";

reg = <0x43c00000 0x1000>;

xlnx,s00-axi-addr-width = <0x4>;

xlnx,s00-axi-data-width = <0x20>;

};

Now, our question is whether this is the right approach or is there a better option for the communication of the PS and the PL? Is editing the device tree allowed? Or is a device tree overlay a better approach?

Thanks in advance.

Best regards,

Quoc Viet Bui

Answer 1

[Charan Jadigam]

Hi,

To communicate between PS and PL using AXI4-lite, Simulink provides support to generate custom IP cores using HDL coder and generate bitstream. You can develop application algorithm using Simulink models and generate c code intended to work on LINUX using Embedded Coder support package for ZYNQ platform.

You can know more about Hardware software co-design workflow here.

Communication between PS and PL using Axi4-lite can be done using AXI-4 interface read/write block in Embedded coder library. The detailed description about process can be found here.