Implementation of median filter on FPGA

Hi everyone, I want to design the median filter on FPGA. I got the output for median filter in matlab and also in matlab simulink. but i want to know how to convert the matlab code or matlab simulink model to hdl code(verilog). Because i am new to matlab please help me to do that. In hdl workflow advisor, they ask test bench how to write the test bench for image processing????

Answer 1

[Bharath Venkataraman]

Here is a link to an example of how to do this in Simulink.

[VANISHREE M]

Thank you for valuable reply. I already read this exampe but still i am not able to generate the veriolg code from simulink. could you please help me to do this further, is there any step by step procedure is there?

Answer 2

[Bharath Venkataraman]

Are you able to generate VHDL (which is the default), or is there an error during HDL code genration?

The last section (Generate HDL Code and Verify Its Behavior) describes how to generate HDL code. You can add a property-value pair to generate Verilog.

makehdl('NoiseRemovalAndImageSharpeningHDL/Pixel-Stream HDL Model','targetLanguage','Verilog')