VHDL code generation and avoiding magic numbers?

Hi,

I would like to avoid magic numbers in my auto-generated VHDL code. Is there a way to neatly generate a pkg.vhdl file of constants using a Simulink model and the HDL Coder tool? Alternatively, is there is a best practice model architecture for generating global constants?

Thanks for reading!

Sara

Answer 1

[Kiran Kintali]

Currently HDLCoder does not have the capaibility of generating all constants into pkg file. Please reach out to [e-mail] to create an enhancement request.